DSC8103 DSC8123
Programmable Low-Jitter Precision LVDS Oscillator
General Description Features
The DSC8103 & DSC8123 series of high Low RMS Phase Jitter: <1 ps (typ)
performance field-programmable oscillators
High Stability: 10, 25, 50 ppm
utilizes a proven silicon MEMS technology to
provide excellent jitter and stability over a Wide Temperature Range
wide range of supply voltages and
o Industrial: -40 to 85 C
temperatures. Using the TIMEFLASH
o Ext. commercial: -20 to 70 C
programmer, the end user can easily
High Supply Noise Rejection: -50 dBc
program the oscillators frequency in the field
for immediate testing or use in advance
Short Lead Time: 2 Weeks
prototype development or production.
Wide Freq. Range: 10 to 460 MHz
DSC8103 has a standby feature allowing it to
Small Industry Standard Footprints
completely power-down when EN pin is
o 2.5x2.0, 3.2x2.5, 5.0x3.2, & 7.0x5.0 mm
pulled low; whereas for DSC8123, only the
Excellent Shock & Vibration Immunity
outputs are disabled when EN is low. Both
o Qualified to MIL-STD-883
oscillators are available in industry standard
2
packages, including the small 3.2x2.5 mm ,
High Reliability
and are drop-in replacement for standard
o 20x better MTF than quartz oscillators
6-pin LVDS quartz oscillators.
Low Current Consumption
Supply Range of 2.25 to 3.6 V
Standby & Output Enable Function
Block Diagram
Lead Free & RoHS Compliant
LVPECL & HCSL Versions Available
Applications
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
Output Enable Modes
HD/SD/SDI Video & Surveillance
EN Pin DSC8103 DSC8123
PCI Express: Gen 1 & Gen 2
High Outputs Active Outputs Active
DisplayPort
NC Outputs Active Outputs Active
Low Standby Outputs Disabled
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DSC8103 | DSC8123 Page 1 MK-Q-B-P-D-030411-03-2
Programmable Low-Jitter Precision LVDS Oscillator
DSC8103 DSC8123
Absolute Maximum Ratings Ordering Code
Item Min Max Unit Condition
Temp Range
E: -20 to 70
Supply Voltage -0.3 +4.0 V
Enable Modes Packing
I: -40 to 85
0: Enable/Standby T: Tape & Reel
L: -40 to 105
Input Voltage -0.3 V +0.3 V
DD
2: Enable/Disable : Tube
M: -55 to 125
Junction Temp - +150 C
Storage Temp -55 +150 C
DSC81 0 3 C I 5 125.0000 T
-
Soldering Temp - +260 C 40sec max.
ESD - V
Package Stability Freq (MHz)
HBM 4000
A: 7.0x5.0mm 1: 50ppm 125.0000
B: 5.0x3.2mm 2: 25ppm
MM 400
C: 3.2x2.5mm 5: 10ppm
CDM 1500
D: 2.5x2.0mm
N: 7.0x5.0mm (no center pad)
Note: 1000+ years of data retention on internal memory
Specifications
Parameter Condition Min. Typ. Max. Unit
1
Supply Voltage V 2.25 3.6 V
DD
EN pin low outputs are disabled
Supply Current I DSC8103 0.095 mA
DD
DSC8123 20 22
Includes frequency variations due
10
Frequency Stability f to initial tolerance, temp. and ppm
25
power supply voltage
50
Aging f 1 year @25C 5 ppm
2
Startup Time t T=25C 5 ms
SU
Input Logic Levels
Input logic high V 0.75xV - V
IH DD
Input logic low V - 0.25xV
IL DD
3
Output Disable Time t 5 ns
DA
DSC8103 5 ms
Output Enable Time t
EN
DSC8123 20 ns
4
Enable Pull-Up Resistor Pull-up resistor exist 40 k
LVDS Outputs
Supply Current I Output Enabled, R =50 29 32 mA
DD L
Output offset Voltage V R=100 Differential 1.125 1.4 V
OS
Delta Offset Voltage V 50 mV
OS
Pk to Pk Output Swing V Single-Ended 350 mV
PP
3
Output Transition time
20% to 80%
Rise Time t 200 ps
R
R =50, C = 2pF
L L
Fall Time t
F
Frequency f Single Frequency 10 460 MHz
0
Output Duty Cycle SYM Differential 48 52 %
Period Jitter J 2.5 ps
PER RMS
200kHz to 20MHz @156.25MHz 0.28
Integrated Phase Noise J 100kHz to 20MHz @156.25MHz 0.4 ps
PH RMS
12kHz to 20MHz @156.25MHz 1.7 2
Notes:
1. Pin 6 V should be filtered with 0.1uf capacitor.
DD
2. t is time to 100ppm of output frequency after V is applied and outputs are enabled.
su DD
3. Output Waveform and Test Circuit figures below define the parameters.
4. Output is enabled if pad is floated or not connected.
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DSC8103 | DSC8123 Page 2 MK-Q-B-P-D-030411-03-2