dsPIC33CH128MP508 FAMILY 28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions Power Management 3V to 3.6V, -40C to +125C: Low-Power Management Modes (Sleep, Idle, Doze) - Master Core: DC to 90 MIPS Integrated Power-on Reset and Brown-out Reset - Slave Core: DC to 100 MIPS High Resolution PWM with Fine Edge Core: Dual 16-Bit dsPIC33CH CPU Placement Master/Slave Core Operation Up to 12 PWM Channels: Independent Peripherals for Master Core and Slave Core - Four channels for Master Dual Partition for Slave PRAM LiveUpdate - Eight channels for Slave Configurable Shared Resources for Master Core 250 ps PWM Resolution and Slave Core Applications Include: Master Core with 64-128 Kbytes of Program - DC/DC Converters Flash with ECC and 16K RAM - AC/DC power supplies Slave Core with 24 Kbytes of Program RAM - Uninterruptable Power Supply (UPS) (PRAM) with ECC and 4K Data Memory RAM - Motor Control: BLDC, PMSM, SR, ACIM Fast 6-Cycle Divide Message Boxes and FIFO to Communicate Timers/Output Compare/Input Capture Between Master and Slave (MSI) Two General Purpose 16-Bit Timers: Code Efficient (C and Assembly) Architecture - One each for Master and Slave 40-Bit Wide Accumulators Peripheral Trigger Generator (PTG) Module: Single-Cycle (MAC/MPY) with Dual Data Fetch - One module for Master Single-Cycle, Mixed-Sign MUL Plus Hardware - Slave can interrupt on select PTG sources Divide 32-Bit Multiply Support - Useful for automating complex sequences Five Sets of Interrupt Context Selected Registers 12 SCCP Modules: and Accumulators per Core for Fast Interrupt - Eight modules for Master Response - Four modules for Slave Zero Overhead Looping - Timer, Capture/Compare and PWM Modes - 16 or 32-bit time base Clock Management - 16 or 32-bit capture Internal Oscillator - 4-deep capture buffer Programmable PLLs and Oscillator Clock - Fully Asynchronous Operation, Available in Sources Sleep Modes Master Reference Clock Output Slave Reference Clock Output Fail-Safe Clock Monitor (FSCM) Fast Wake-up and Start-up Backup Internal Oscillator LPRC Oscillator 2017-2018 Microchip Technology Inc. DS70005319B-page 1dsPIC33CH128MP508 FAMILY Advanced Analog Features Other Features Four ADC Modules: PPS to Allow Function Remap - One module for Master core Programmable Cyclic Redundancy Check (CRC) for the Master - Three modules for Slave core Two SENT Modules for the Master - 12-bit, 3.5 Msps ADC - Up to 18 conversion channels Direct Memory Access (DMA) Four DAC/Analog Comparator Modules: - One module for Master core Eight DMA Channels: - Three modules for Slave core - Six DMA channels available for the Master core - 12-bit DACs with hardware slope - Two DMA channels available for the Slave core compensation - 15 ns analog comparators Debugger Development Support Three PGA Modules: In-Circuit and In-Application Programming - Three modules for Slave core Simultaneous Debugging Support for Master and - Can be read by Master ADC Slave Cores - Option to interface with Master ADC Master Only Debug and Slave Only Debug Shared DAC/Analog Output: Support - DAC/analog comparator outputs Master with Three Complex, Five Simple - PGA outputs Breakpoints and Slave with One Complex, Two Simple Breakpoints IEEE 1149.2 Compatible (JTAG) Boundary Scan Communication Interfaces Trace Buffer and Run-Time Watch Three UART Modules: - Two modules for Master core Safety Features - One module for Slave core DMT (Deadman Timer) - Support for DMX, LIN/J2602 protocols and IrDA ECC (Error Correcting Code) 2 Three 4-Wire SPI/I S Modules: WDT (Watchdog Timer) - Two modules for Master core CodeGuard Security - One module for Slave core CRC (Cyclic Redundancy Check) CAN Flexible Data-Rate (FD) Module for the Two-Speed Start-up Master Core Fail-Safe Clock Monitoring 2 Three I C Modules: Backup FRC (BFRC) - Two modules for Master Capless Internal Voltage Regulator - One module for Slave Virtual Pins for Redundancy and Monitoring - Support for SMBus DS70005319B-page 2 2017-2018 Microchip Technology Inc.