dsPIC33CK32MP503-I/M5 Microchip

dsPIC33CK256MP508 FAMILY 28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions Power Management 3.0V to 3.6V, -40C to +85C, DC to 100 MIPS Low-Power Management Modes (Sleep, Idle, Doze) 3.0V to 3.6V, -40C to +125C, DC to 100 MIPS Integrated Power-on Reset and Brown-out Reset Core: 16-Bit dsPIC33CK CPU High-Speed PWM 32-256 Kbytes of Program Flash with ECC and 8-24K RAM 8 PWM Pairs Fast 6-Cycle Divide Up to 250 ps PWM Resolution LiveUpdate Dead Time for Rising and Falling Edges Code Efficient (C and Assembly) Architecture Dead-Time Compensation 40-Bit Wide Accumulators Clock Chopping for High-Frequency Operation Single-Cycle (MAC/MPY) with Dual Data Fetch PWM Support for: Single-Cycle, Mixed-Sign MUL Plus - DC/DC, AC/DC, inverters, PFC, lighting Hardware Divide - BLDC, PMSM, ACIM, SRM motors 32-Bit Multiply Support Fault and Current Limit Inputs Four Sets of Interrupt Context Saving Registers Flexible Trigger Configuration for ADC Triggering which Include Accumulator and STATUS for Fast Interrupt Handling Timers/Output Compare/Input Capture Zero Overhead Looping One General Purpose Timer RAM Memory Built-In Self-Test (MBIST) Peripheral Trigger Generator (PTG): - Up to 15 trigger sources to other Clock Management peripheral modules Internal Oscillator - CPU independent state machine-based Programmable PLLs and Oscillator Clock Sources instruction sequencer Reference Clock Output Nine MCCP/SCCP modules which Include Timer, Fail-Safe Clock Monitor (FSCM) Capture/Compare and PWM: Fast Wake-up and Start-up - 1 MCCP Backup Internal Oscillator - 8 SCCPs - 16 or 32-bit time base - 16 or 32-bit capture - 4-deep capture buffer Fully Asynchronous Operation, Available in Sleep Modes 2017-2018 Microchip Technology Inc. Advance Information DS70005349B-page 1dsPIC33CK256MP508 FAMILY Advanced Analog Features Direct Memory Access (DMA) High-Speed ADC module: Four DMA Channels - 12-bit with two dedicated SAR ADC cores and one shared SAR ADC core Debugger Development Support - Configurable resolution (up to 12-bit) for each In-Circuit and In-Application Programming and ADC core Debugging - Up to 3.5 Msps conversion rate per channel Three Complex, Five Simple Breakpoints at 12-bit resolution IEEE 1149.2 Compatible (JTAG) Boundary Scan - Up to 24 input channels Trace Buffer and Run-Time Watch - Dedicated result buffer for each analog channel - Flexible and independent ADC trigger sources Safety Features - Four digital comparators Clock Monitor System with Backup Oscillator - Four oversampling filters for increased resolution DMT (Deadman Timer) Up to Three Analog Comparators: ECC (Error Correcting Code) - 15 ns analog comparator WDT (Watchdog Timer) Up to Three Op Amps CodeGuard Security Three 12-Bit DACs: CRC (Cyclic Redundancy Check) - Hardware slope compensation ICSP Write Inhibit RAM Memory Built-In Self-Test (MBIST) Communication Interfaces Three Protocol UARTs with Automated Protocol Qualification and Class B Support Handling Support for: AEC-Q100 REVG (Grade 1: -40C to +125C) - LIN 2.2 Compliant -DMX Class B Safety Library, IEC 60730 -IrDA 2 Three 4-Wire SPI/I S modules CAN Flexible Data (FD) module 2 Three I C modules with SMBus Support PPS to Allow Function Remap Programmable Cyclic Redundancy Check (CRC) Two SENT modules Parallel Master Port (PMP) DS70005349B-page 2 Advance Information 2017-2018 Microchip Technology Inc.