dsPIC33CK64MC105 FAMILY 16-Bit Digital Signal Controllers with High-Speed ADC, Op Amps, Comparators and High-Resolution PWM Operating Conditions Microcontroller Features 3.0V to 3.6V: -40C to +125C, DC to 100 MIPS Small Pin Count Packages Ranging from 28 to 48 Pins, Including UQFN as Small as 4x4 mm 3.0V to 3.6V: -40C to +150C, DC to 70 MIPS High-Current I/O Sink/Source Edge or Level Change Notification Interrupt on High-Performance 16-Bit DSP RISC CPU I/O Pins 16-Bit Wide Data Path Peripheral Pin Select (PPS) Remappable Pins Code Efficient (C and Assembly) Architecture Up to 64 Kbytes Flash Memory: 40-Bit Wide Accumulators - 10,000 erase/write cycle endurance Single-Cycle (MAC/MPY) with Dual Data Fetch - 20 years minimum data retention Single-Cycle, Mixed-Sign Multiply: - Self-programmable under software control - 32-bit multiply support - Programmable code protection Fast Six-Cycle Divide - Error Code Correction (ECC) Zero Overhead Looping - Flash OTP by ICSP Write Inhibit Eight Kbytes SRAM Memory: High-Resolution PWM - SRAM Memory Built-In Self-Test (MBIST) Four PWM Pairs Multiple Interrupt Vectors with Individually Up to 2 ns PWM Resolution Programmable Priority Dead Time for Rising and Falling Edges Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Dead-Time Compensation Reserved Interrupt Handling Clock Chopping for High-Frequency Operation Four External Interrupt Pins PWM Support for: Watchdog Timer (WDT) - DC/DC, AC/DC, inverters, PFC, lighting Windowed Deadman Timer (DMT) - BLDC, PMSM, ACIM, SRM motors Fail-Safe Clock Monitor (FSCM) with Dedicated Fault and Current Limit Inputs Oscillator Flexible Trigger Configuration for ADC Triggering Selectable Oscillator Options Including: - High-precision, 8 MHz internal Fast RC High-Speed Analog-to-Digital Converter (FRC) Oscillator Up to 15 A/D inputs - Primary high-speed, crystal/resonator 12-Bit Resolution oscillator or external clock One Shared SAR ADC Core - Primary PLL, which can be clocked from FRC or crystal oscillator Up to 3.5 Msps Conversion Rate per Core Low-Power Management modes (Sleep and Idle) Dedicated Result Buffer for Each Analog Channel Power-on Reset and Brown-out Reset Flexible and Independent ADC Trigger Sources On-Board Capacitorless Regulator Four Digital Comparators 384 Bytes of One-Time-Programmable (OTP) Four Oversampling Filters Memory 2019-2021 Microchip Technology Inc. DS70005399D-page 1dsPIC33CK64MC105 FAMILY Peripheral Features Debug Features Two Four-Wire SPI modules (up to 50 Mbps): Three Programming and Debugging Interfaces: - 16-byte FIFO - Two-wire ICSP interface with non-intrusive access and real-time data exchange with - Variable width 2 application -I S mode Three Complex, Five Simple Breakpoints 2 One I C Host and Client w/Address Masking and IEEE Standard 1149.2 Compatible (JTAG) IPMI Support Boundary Scan Three Protocol UARTs with Automated Handling Support for: Safety Features - LIN 2.2 -DMX Backup Fast RC Oscillator (BFRC) - Smart card (ISO 7816) Brown-out Reset (BOR) One SENT module Capless Internal Voltage Regulator Timers/Counters: Clock Monitor System with Backup Oscillator - One dedicated 16-bit timer/counter CodeGuard Security Four Single Output Capture/Compare/PWM/ Cyclic Redundancy Check (CRC) Timer (SCCP) modules: Dual Watchdog Timer (WDT) - Flexible configuration as PWM, input capture, Fail-Safe Clock Monitoring (FSCM) output compare or timers Flash Error Correcting Code (ECC) - Two 16-bit timers or one 32-bit timer in each Flash OTP by ICSP Write Inhibit module RAM Memory Built-In Self-Test (MBIST) - PWM resolution down to 2.5 ns Two-Speed Start-up - Single PWM output Virtual Pins for Redundancy and Monitoring One Quadrature Encoder Interface (QEI): Windowed Deadman Timer (DMT) - Four inputs: Phase A, Phase B, Home, Index - One 32-bit timer/counter (in QEI module, Functional Safety Collaterals available if encoder is not used) Class B Safety Library IEC 60730 Reference Clock Output (REFCLKO) Four Configurable Logic Cells (CLC) with Internal For ASIL B and Beyond Applications ISO 26262 Connections to Select Peripherals and PPS FMEDA Computation Spreadsheet (evaluation of Four-Channel Hardware DMA Random Hardware Failures Metric) Functional Safety Manual 32-Bit CRC Calculation module Functional Safety Diagnostics Suite Peripheral Trigger Generator (PTG): - 16 possible trigger sources to other Qualification peripheral modules - CPU-independent state machine-based AEC-Q100 REV G (Grade 1: -40C to +125C) instruction sequencer AEC-Q100 REV G (Grade 0: -40C to +150C) - Two 16-bit general purpose timers Analog Features One Fast Analog Comparator with Input Multiplexing Three Operational Amplifiers One 12-Bit PDM DAC with Slope Compensation One Output DAC Buffer DS70005399D-page 2 2019-2021 Microchip Technology Inc.