DSPIC33CK64MP105-I/M4 Microchip

dsPIC33CK64MP105 FAMILY 16-Bit Digital Signal Controllers with High-Speed ADC, Op Amps, Comparators and High-Resolution PWM Operating Conditions Microcontroller Features 3.0V to 3.6V: -40C to +125C, DC to 100 MHz Small Pin Count Packages Ranging from 28 to 48 Pins, Including UQFN as Small as 4x4 mm High-Current I/O Sink/Source High-Performance 16-Bit DSP RISC CPU Edge or Level Change Notification Interrupt on 16-Bit Wide Data Path I/O Pins Code Efficient (C and Assembly) Architecture Peripheral Pin Select (PPS) Remappable Pins 40-Bit Wide Accumulators Up to 64 Kbytes Flash Memory: Single-Cycle (MAC/MPY) with Dual Data Fetch - 10,000 erase/write cycle endurance Single-Cycle, Mixed-Sign Multiply: - 20 years minimum data retention - 32-bit multiply support - Self-programmable under software control Fast 6-Cycle Divide - Programmable code protection Zero Overhead Looping - Error Code Correction (ECC) - ICSP Write Inhibit High-Speed PWM Eight Kbytes SRAM Memory: Four PWM Pairs - SRAM Memory Built-In Self-Test (MBIST) Up to 250 ps PWM Resolution Multiple Interrupt Vectors with Individually Dead Time for Rising and Falling Edges Programmable Priority Dead-Time Compensation Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Clock Chopping for High-Frequency Operation Interrupt Handling PWM Support for: Four External Interrupt Pins - DC/DC, AC/DC, inverters, PFC, lighting Watchdog Timer (WDT) - BLDC, PMSM, ACIM, SRM motors Windowed Deadman Timer (DMT) Fault and Current Limit Inputs Fail-Safe Clock Monitor (FSCM) with Dedicated Flexible Trigger Configuration for ADC Triggering Oscillator for Backup Selectable Oscillator Options Including: High-Speed Analog-to-Digital Converter - Low-Power 32 kHz RC (LPRC) Oscillator 12-Bit Resolution - High-precision, 8 MHz internal Fast RC Two Dedicated SAR ADC Cores and One Shared (FRC) Oscillator SAR ADC Core - Primary high-speed, crystal/resonator Up to 3.5 Msps Conversion Rate per Core oscillator or external clock Dedicated Result Buffer for Each Analog Channel - Primary PLL, which can be clocked from FRC Flexible and Independent ADC Trigger Sources or crystal oscillator Four Digital Comparators - Secondary/Alternate PLL (APLL) for PWM and ADC Four Oversampling Filters Low-Power Management modes (Sleep and Idle) Power-on Reset and Brown-out Reset Programmable High/Low-Voltage Detect (HLVD) On-Board Capacitorless Regulator 256 Bytes of One-Time-Programmable (OTP) Memory 2018-2019 Microchip Technology Inc. DS70005363B-page 1dsPIC33CK64MP105 FAMILY Peripheral Features Analog Features Three 4-Wire SPI modules (up to 50 Mbps): Three Fast Analog Comparators with Input Multiplexing - 16-byte FIFO Three Operational Amplifiers - Variable width 2 Three 12-Bit PDM DACs with -I S mode Slope Compensation 2 Two I C Master and Slave w/Address Masking One Output DAC Buffer and IPMI Support Three Protocol UARTs with Automated Handling Qualification and Class B Support Support for: - LIN 2.2 AEC-Q100 REVG (Grade 1: -40C to +125C) -DMX Class B Safety Library, IEC 60730 - Smart card (ISO 7816) -IrDA Debug Features Two SENT modules Three Programming and Debugging Interfaces: One Dedicated 16-Bit Timer/Counter - 2-wire ICSP interface with non-intrusive Four Single Output Capture/Compare/PWM/ access and real-time data exchange with Timer (SCCP) modules: application - Flexible configuration as PWM, input capture, Three Complex, Five Simple Breakpoints output compare or timers IEEE Standard 1149.2 Compatible (JTAG) - Two 16-bit timers or one 32-bit timer in each Boundary Scan module - PWM resolution down to 4 ns - Single PWM output One Multiple Output Capture/Compare/PWM/ Timer (MCCP) module: - Flexible configuration as PWM, input capture, output compare or timers - Two 16-bit timers or one 32-bit timer in each module - PWM resolution down to 4 ns - Up to six PWM outputs - Programmable dead time - Auto-shutdown Two Quadrature Encoder Interfaces (QEI): - Four inputs: Phase A, Phase B, Home, Index Reference Clock Output (REFCLKO) Four Configurable Logic Cells (CLC) with Internal Connections to Select Peripherals and PPS 4-Channel Hardware DMA 32-Bit CRC Calculation module Peripheral Trigger Generator (PTG): - 16 possible trigger sources to other peripheral modules - CPU independent state machine-based instruction sequencer DS70005363B-page 2 2018-2019 Microchip Technology Inc.