dsPIC33EPXXXGS70X/80X dsPIC33EPXXXGS70X/80X Family Silicon Errata and Data Sheet Clarification The dsPIC33EPXXXGS70X/80X family devices that For example, to identify the silicon revision level you have received conform functionally to the current using MPLAB IDE in conjunction with a hardware Device Data Sheet (DS70005258C), except for the debugger: anomalies described in this document. 1. Using the appropriate interface, connect the The silicon issues discussed in the following pages are device to the hardware debugger. for silicon revisions with the Device and Revision IDs 2. Open an MPLAB IDE project. listed in Table 1. The silicon issues are summarized in 3. Configure the MPLAB IDE project for the Table 2. appropriate device and hardware debugger. The errata described in this document will be addressed 4. Based on the version of MPLAB IDE you are in future revisions of the dsPIC33EPXXXGS70X/80X using, do one of the following: silicon. a) For MPLAB IDE8, select Programmer > Reconnect. Note: This document summarizes all silicon errata issues from all revisions of silicon, b) For MPLAB X IDE, select Window > Dash- previous as well as current. Only the issues board and click the Refresh Debug Tool indicated in the last column of Table 2 Status icon ( ). apply to the current silicon revision (B0). 5. Depending on the development tool used, the part number and Device Revision ID value Data Sheet clarifications and corrections start on appear in the Output window. page 15, following the discussion of silicon issues. Note: If you are unable to extract the silicon The silicon revision level can be identified using the revision level, please contact your local current version of MPLAB IDE and Microchips pro- Microchip sales office for assistance. grammers, debuggers, and emulation tools, which are available at the Microchip corporate website The DEVREV values for the various (www.microchip.com). dsPIC33EPXXXGS70X/80X silicon revisions are shown in Table 1. TABLE 1: SILICON DEVREV VALUES Revision ID for Revision ID for (2) (2) (1) Silicon Revision (1) Silicon Revision Part Number Device ID Part Number Device ID A2 B0 A2 B0 dsPIC33EP64GS708 0x6C03 dsPIC33EP128GS705 0x6C30 dsPIC33EP64GS804 0x6C40 dsPIC33EP128GS706 0x6C12 dsPIC33EP64GS805 0x6C60 dsPIC33EP128GS708 0x6C13 dsPIC33EP64GS806 0x6C42 0x4001 0x4002 dsPIC33EP128GS804 0x6C50 0x4001 0x4002 dsPIC33EP64GS808 0x6C43 dsPIC33EP128GS805 0x6C70 dsPIC33EP128GS702 0x6C11 dsPIC33EP128GS806 0x6C52 dsPIC33EP128GS704 0x6C10 dsPIC33EP128GS808 0x6C53 Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configu- ration memory space. They are shown in hexadecimal in the format DEVID DEVREV. 2: Refer to the dsPIC33EPXXXGS70X/80X Family Flash Programming Specification (DS70005256) for detailed information on Device and Revision IDs for your specific device. 2017-2022 Microchip Technology Inc. and its subsidiaries DS80000722J-page 1dsPIC33EPXXXGS70X/80X TABLE 2: SILICON ISSUE SUMMARY Affected (1) Item Revisions Module Feature Issue Summary Number A2 B0 CPU div.sd 1. When using the signed 32-by-16-bit division instruction, XX div.sd, the Overflow bit is not getting set when an overflow occurs. CPU Variable Interrupt 2. When Variable Interrupt Latency is selected (VAR = 1), an XX Latency address error trap or incorrect application behavior may occur. CPU DO Loop 3. PSV access, including Table Reads or Writes in the last XX instruction of a DO loop, is not allowed. ADC ADC Sampling 4. Under specific conditions, multi-core ADC sampling XX crosstalk noise might be present. ADC Oversampling 5. Parallel operation of the two oversampling filters results in XX Filter missing data writes to the lower priority Filter Data Result register. ADC DNL 6. DNL is out of specification at the mid-code boundary in XX Single-Ended mode. UART Break 7. The Transmit Shift Register Empty (TRMT) bit is unreliable XX Character when there are back-to-back Break character transmissions. Generation 2 I C Client Mode 8. The 7-bit address that matches the 10-bit upper address X value (111 10xx) can never be accepted, regardless of the STRICT bit. 2 I C Client Mode 9. When data hold is enabled and software sends a NACK, a XX Client interrupt is occurring after the 9th clock. SPI Audio 10. At start-up, the Idle state of the SDOx pin depends on the XX MSB of the first data packet when the Client is configured for Left/Right Justified mode. SPI Audio 11. In PCM/DSP mode, if the channel width is greater than data XX width, the data loaded are not transmitted as per the loading sequence. SPI Audio 12. In PCM/DSP mode, if the channel width is greater than data XX width, the state of SDOx is latched to the LSB of the data transmitted. PTG Debug 13. Single-stepping of the command sequence queue when XX device is in Debug mode is not functional. PTG PTGADD/ 14. PTGADD and PTGCOPY commands do not change the counter XX PTGCOPY limit values. PTG Software 15. Software trigger (PTGSWT) is not cleared by hardware. X X Trigger PWM Module Enable 16. A glitch may be observed on the PWM pins when the PWM XX module is enabled after assignment of pin ownership to the PWM module. PWM Center-Aligned 17. Dead time between transitions of the PWMxH and PWMxL XX Complementary outputs may not be asserted when Swap mode is disabled. PWM Master Time 18. Changes to the PHASEx register after enabling the PWM XX Base Mode module may result in abnormal PWM switching waveforms. PWM Push-Pull Mode 19. When EIPU = 1, Period register writes may produce XX back-to-back pulses under certain conditions. Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80000722J-page 2 2017-2022 Microchip Technology Inc. and its subsidiaries