dsPIC33EPXXGS202 FAMILY 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators Operating Conditions Advanced Analog Features 3.0V to 3.6V, -40C to +85C, DC to 70 MIPS High-Speed ADC module: 3.0V to 3.6V, -40C to +125C, DC to 60 MIPS - 12-bit with 2 dedicated SAR ADC cores and one shared SAR ADC core Flash Architecture - Up to 3.25 Msps conversion rate per ADC core 12-bit resolution 16 Kbytes-32 Kbytes of Program Flash - Dedicated result buffer for each analog channel Core: 16-Bit dsPIC33E CPU - Flexible and independent ADC trigger Code-Efficient (C and Assembly) Architecture sources Two 40-Bit Wide Accumulators - Two digital comparators Single-Cycle (MAC/MPY) with Dual Data Fetch - One oversampling filter Single-Cycle Mixed-Sign MUL Plus Two Rail-to-Rail Comparators with Hysteresis: Hardware Divide - Dedicated 12-bit Digital-to-Analog Converter 32-Bit Multiply Support (DAC) for each analog comparator Two Additional Working Register Sets (reduces Two Programmable Gain Amplifiers: context switching) - Single-ended or independent ground reference Clock Management - Five selectable gains (4x, 8x, 16x, 32x 0.9% Internal Oscillator and 64x) Programmable PLLs and Oscillator Clock Sources - 40 MHz gain bandwidth Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Interconnected SMPS Peripherals Fast Wake-up and Start-up Reduces CPU Interaction to Improve Performance Flexible PWM Trigger Options for Power Management ADC Conversions Low-Power Management modes (Sleep, High-Speed Comparator Truncates PWM Idle, Doze) (15 ns typical): Integrated Power-on Reset and Brown-out Reset - Supports Cycle-by-Cycle Current mode control 0.5 mA/MHz Dynamic Current (typical) - Current Reset mode (variable frequency) 10 A IPD Current (typical) Timers/Output Compare/Input Capture High-Speed PWM Three 16-Bit and up to Two 32-Bit Timers/ Three PWM Generators (two outputs per Counters generator) One Output Compare (OC) module, Configurable Individual Time Base and Duty Cycle for each PWM as Timers/Counters 1.04 ns PWM Resolution (frequency, duty cycle, One Input Capture (IC) module dead time and phase) Supports Center-Aligned, Redundant, Complementary and True Independent Output modes Independent Fault and Current-Limit Inputs Output Override Control PWM Support for: - AC/DC, DC/DC, inverters, PFC, lighting 2015-2016 Microchip Technology Inc. DS70005208D-page 1dsPIC33EPXXGS202 FAMILY Communication Interfaces Qualification and Class B Support One UART module (15 Mbps): AEC-Q100 REVG (Grade 1, -40C to +125C) - Supports LIN/J2602 protocols and IrDA Class B Safety Library, IEC 60730 One 4-Wire SPI module (15 Mbps) 4x4x0.6 mm and 6x6x0.5 mm UQFN Packages 2 are Designed and Optimized to ease IPC9592B One I C module (up to 1 Mbaud) with SMBus 2nd Level Temperature Cycle Qualification Support Debugger Development Support Input/Output In-Circuit and In-Application Programming Sink/Source up to 12mA/15mA, respectively Pin-Specific for Standard VOH/VOL Three Program and One Complex Data Breakpoint 5V Tolerant Pins IEEE 1149.2 Compatible (JTAG) Boundary Scan Selectable Open-Drain, Pull-ups and Pull-Downs Trace and Run-Time Watch External Interrupts on All I/O Pins Peripheral Pin Select (PPS) to allow Function Remap with Six Virtual I/Os TABLE 1: dsPIC33EPXXGS202 FAMILY DEVICES Remappable Peripherals Device dsPIC33EP16GS202 28 16K 2K 3 1 1 1 1 3 3x2 12 1 3 2 2 21 SSOP, SOIC, QFN-S, UQFN (4x4 mm), dsPIC33EP32GS202 28 32K 2K 3 1 1 1 1 3 3x2 12 1 3 2 2 21 UQFN (6x6 mm) Note 1: The external clock for Timer1, Timer2 and Timer3 is remappable. 2: INT0 is not remappable INT1 and INT2 are remappable. DS70005208D-page 2 2015-2016 Microchip Technology Inc. Pins Program Memory Bytes RAM Bytes (1) Timers Input Capture Output Compare UART SPI (2) External Interrupts PWM ADC Inputs 2 I C ADC Cores PGA Analog Comparator General Purpose I/O (GPIO) Packages