dsPIC33EPXXXGS70X/80X FAMILY 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators Operating Conditions Advanced Analog Features 3.0V to 3.6V, -40C to +85C, DC to 70 MIPS High-Speed ADC module: 3.0V to 3.6V, -40C to +125C, DC to 60 MIPS - 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core Flash Architecture - Configurable resolution (up to 12-bit) for each ADC core Dual Partition Flash Program Memory with Live Update: - Up to 3.25 Msps conversion rate per channel at 12-bit resolution - Supports programming while operating - 11 to 22 single-ended inputs - Supports partition soft swap - Dedicated result buffer for each analog channel Core: 16-Bit dsPIC33E CPU - Flexible and independent ADC trigger sources Code-Efficient (C and Assembly) Architecture - Two digital comparators Two 40-Bit Wide Accumulators - Two oversampling filters for increased Single-Cycle (MAC/MPY) with Dual Data Fetch resolution Single-Cycle Mixed-Sign MUL plus Four Rail-to-Rail Comparators with Hysteresis: Hardware Divide - Dedicated 12-bit Digital-to-Analog Converter 32-Bit Multiply Support (DAC) for each analog comparator Four Additional Working Register Sets (reduces - Up to two DAC reference outputs context switching) - Up to two external reference inputs Two Programmable Gain Amplifiers: Clock Management - Single-ended or independent ground reference 0.9% Internal Oscillator - Five selectable gains (4x, 8x, 16x, 32x and 64x) Programmable PLLs and Oscillator Clock Sources - 40 MHz gain bandwidth Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Interconnected SMPS Peripherals Fast Wake-up and Start-up Reduces CPU Interaction to Improve Performance Flexible PWM Trigger Options for Power Management ADC Conversions Low-Power Management modes (Sleep, High-Speed Comparator Truncates PWM Idle, Doze) (15 ns typical): Integrated Power-on Reset and Brown-out Reset - Supports Cycle-by-Cycle Current mode control 0.5 mA/MHz Dynamic Current (typical) - Current Reset mode (variable frequency) 20 A IPD Current (typical) Timers/Output Compare/Input Capture High-Speed PWM Five 16-Bit and up to Two 32-Bit Timers/Counters Eight PWM Generators (two outputs per generator) Four Output Compare (OC) modules, Configurable Individual Time Base and Duty Cycle for each PWM as Timers/Counters 1.04 ns PWM Resolution (frequency, duty cycle, Four Input Capture (IC) modules dead time and phase) Supports Center-Aligned, Redundant, Complementary and True Independent Output modes Independent Fault and Current-Limit Inputs Output Override Control PWM Support for AC/DC, DC/DC, Inverters, PFC and Lighting 2016-2017 Microchip Technology Inc. DS70005258B-page 1dsPIC33EPXXXGS70X/80X FAMILY Communication Interfaces Qualification and Class B Support Two UART modules (15 Mbps): AEC-Q100 REVG (Grade 1, -40C to +125C) - Supports LIN/J2602 protocols and IrDA Class B Safety Library, IEC 60730 Three Variable Width SPI modules with Operating The 6x6x0.55 mm UQFN Package is Designed modes: and Optimized to ease IPC9592B 2nd Level Temperature Cycle Qualification - 3-wire SPI - 8x16 or 8x8 FIFO mode 2 Debugger Development Support -I S mode 2 Two I C modules (up to 1 Mbaud) with SMBus In-Circuit and In-Application Programming Support Five Program and Three Complex Up to Two CAN modules Data Breakpoints Four-Channel DMA IEEE 1149.2 Compatible (JTAG) Boundary Scan Trace and Run-Time Watch Input/Output Constant-Current Source (10 A nominal) Digital Peripherals Sink/Source up to 12 mA/15 mA, respectively Four Configurable Logic Cells Pin-Specific for Standard VOH/VOL Peripheral Trigger Generator 5V Tolerant Pins Selectable, Open-Drain Pull-ups and Pull-Downs External Interrupts on all I/O Pins Peripheral Pin Select (PPS) to allow Function Remap with Six Virtual I/Os 12-Bit Remappable Peripherals ADC Device dsPIC33EP128GS702 28 128K 8K 20 5 4 4 2 3 8x2 4 0 1 2 4 1 11 5 2041 1 SOIC, QFN-S, UQFN dsPIC33EP64GS804 44 64K 8K33 5 4 4 2 3 8x24 2 1 2 4 1 17 5 2441 1 QFN, dsPIC33EP128GS704 44 128K 8K 33 5 4 4 2 3 8x2 4 0 1 2 4 1 17 5 2041 1 TQFP dsPIC33EP128GS804 44 128K 8K 33 5 4 4 2 3 8x2 4 2 1 2 4 1 17 5 2441 1 dsPIC33EP64GS805 48 64K 8K33 5 4 4 2 3 8x24 2 1 2 4 1 17 5 2441 1 dsPIC33EP128GS705 48 128K 8K 33 5 4 4 2 3 8x2 4 0 1 2 4 1 17 5 2041 1 TQFP dsPIC33EP128GS805 48 128K 8K 33 5 4 4 2 3 8x2 4 2 1 2 4 1 17 5 2441 1 dsPIC33EP64GS806 64 64K 8K51 5 4 4 2 3 8x24 2 1 2 4 1 22 5 2442 1 dsPIC33EP128GS706 64 128K 8K 51 5 4 4 2 3 8x2 4 0 1 2 4 1 22 5 2042 1 TQFP dsPIC33EP128GS806 64 128K 8K 51 5 4 4 2 3 8x2 4 2 1 2 4 1 22 5 2442 1 dsPIC33EP64GS708 80 64K 8K67 5 4 4 2 3 8x24 0 1 2 4 1 22 5 2042 1 dsPIC33EP64GS808 80 64K 8K67 5 4 4 2 3 8x24 2 1 2 4 1 22 5 2442 1 TQFP dsPIC33EP128GS708 80 128K 8K 67 5 4 4 2 3 8x2 4 0 1 2 4 1 22 5 2042 1 dsPIC33EP128GS808 80 128K 8K 67 5 4 4 2 3 8x2 4 2 1 2 4 1 22 5 2442 1 Note 1: The external clock for Timer1, Timer2 and Timer3 is remappable. 2: PWM4 through PWM8 are remappable on 28/44/48-pin devices on 64-pin devices, only PWM7/PWM8 are remappable. 3: External interrupts, INT0 and INT4, are not remappable. DS70005258B-page 2 2016-2017 Microchip Technology Inc. Pins Program Memory Bytes RAM (Bytes) General Purpose I/O (GPIO) (1) Timers Input Capture Output Compare UART SPI (2) PWM (3) External Interrupts CAN Reference Clock 2 I C CLC PTG Analog Inputs S&H Circuits PGA DMA Analog Comparator DAC Output Constant-Current Source Packages