dsPIC33EV128GM004-IPT Microchip

dsPIC33EVXXXGM00X/10X FAMILY 16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features Operating Conditions PWM 4.5V to 5.5V, -40C to +85C, DC to 70 MIPS Up to Six Pulse-Width Modulation (PWM) Outputs (three generators) 4.5V to 5.5V, -40C to +125C, DC to 60 MIPS Primary Master Time Base Inputs allow 4.5V to 5.5V, -40C to +150C, DC to 40 MIPS Time Base Synchronization from Internal/External Sources Core: 16-Bit dsPIC33E CPU Dead Time for Rising and Falling Edges Code-Efficient (C and Assembly) Architecture 7.14 ns PWM Resolution 16-Bit Wide Data Path PWM Support for: Two 40-Bit Wide Accumulators - DC/DC, AC/DC, inverters, Power Factor Single-Cycle (MAC/MPY) with Dual Data Fetch Correction (PFC) and lighting Single-Cycle, Mixed-Sign MUL plus Hardware - Brushless Direct Current (BLDC), Permanent Divide Magnet Synchronous Motor (PMSM), 32-Bit Multiply Support AC Induction Motor (ACIM), Switched Reluctance Motor (SRM) Intermediate Security for Memory: - Programmable Fault inputs - Provides a Boot Flash Segment in addition to the existing General Flash Segment - Flexible trigger configurations for Analog-to-Digital conversion Error Code Correction (ECC) for Flash - Supports PWM lock, PWM output chopping Added Two Alternate Register Sets for Fast and dynamic phase shifting Context Switching Advanced Analog Features Clock Management ADC module: Internal, 15% Low-Power RC (LPRC) 32 kHz - Configurable as 10-bit, 1.1 Msps with Internal, 1% Fast RC (FRC) 7.37 MHz four S&H or 12-bit, 500 ksps with one S&H Internal, 10% Backup FRC (BFRC) 7.37 MHz - Up to 36 analog inputs Programmable PLLs and Oscillator Clock Sources Flexible and Independent ADC Trigger Sources Fail-Safe Clock Monitor (FSCM) Up to Four Op Amp/Comparators with Direct Additional FSCM Source (BFRC), Intended to Connection to the ADC module: Provide a Clock Fail Switch Source for the - Additional dedicated comparator and System Clock 7-bit Digital-to-Analog Converter (DAC) Independent Watchdog Timer (WDT) - Two comparator voltage reference outputs System Windowed Watchdog Timer (DMT) - Programmable references with 128 voltage Fast Wake-up and Start-up points - Programmable blanking and filtering Power Management Charge Time Measurement Unit (CTMU): Low-Power Management modes (Sleep, Idle - Supports mTouch capacitive touch sensing and Doze) - Provides high-resolution time Power Consumption Minimized Executing measurement (1 ns) NOP String - On-chip temperature measurement Integrated Power-on Reset (POR) and Brown-out - Temperature sensor diode Reset (BOR) - Nine sources of edge input triggers (CTED1, 0.5 mA/MHz Dynamic Current (typical) CTED2, OCPWM, TMR1, SYSCLK, OSCLK, 50 A at +25C IPD Current (typical) FRC, BFRC and LPRC) 2013-2016 Microchip Technology Inc. DS70005144E-page 1dsPIC33EVXXXGM00X/10X FAMILY Timers/Output Compare/Input Capture Input/Output Nine General Purpose Timers: GPIO Registers to Support Selectable Slew Rate I/Os - Five 16-bit and up to two 32-bit timers/counters Timer3 can provide ADC Peripheral Pin Select (PPS) to allow Function trigger Remap Four Output Compare modules Configurable as Sink/Source: 8 mA or 12 mA, Pin-Specific for Timers/Counters Standard VOH/VOL Four Input Capture modules Selectable Open-Drain, Pull-ups and Pull-Downs Change Notice Interrupts on All I/O Pins Communication Interfaces Qualification and Class B Support Two Enhanced Addressable Universal Asynchronous Receiver/Transmitter (UART) AEC-Q100 REVG (Grade 1: -40C to +125C) modules (6.25 Mbps): Compliant - With support for LIN/J2602 bus and IrDA AEC-Q100 REVG (Grade 0: -40C to +150C) - High and low speed (SCI) Compliant Two SPI modules (15 Mbps): Class B Safety Library, IEC 60730 - 25 Mbps data rate without using PPS 2 Class B Fault Handling Support One I C module (up to 1 Mbaud) with SMBus Support Backup FRC Two SENT J2716 (Single-Edge Nibble Windowed WDT uses LPRC Transmission-Transmit/Receive) module for Windowed Deadman Timer (DMT) uses System Automotive Applications Clock (System Windowed Watchdog Timer) One CAN module: H/W Clock Monitor Circuit - 32 buffers, 16 filters and three masks Oscillator Frequency Monitoring through CTMU (OSCI, SYSCLK, FRC, BFRC, LPRC) Direct Memory Access (DMA) Dedicated PWM Fault Pin 4-Channel DMA with User-Selectable Priority Lockable Clock Configuration Arbitration UART, Serial Peripheral Interface (SPI), ADC, Debugger Development Support Input Capture, Output Compare and Controller In-Circuit and In-Application Programming Area Network (CAN) Three Complex and Five Simple Breakpoints Trace and Run-Time Watch DS70005144E-page 2 2013-2016 Microchip Technology Inc.