dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16-Bit Digital Signal Controllers (up to 16-Kbyte Flash and up to 2-Kbyte SRAM) with High-Speed PWM, ADC and Comparators Operating Conditions Advanced Analog Features (Continued) 3.0V to 3.6V, -40C to +150C, DC to 20 MIPS Up to Four High-Speed Comparators with Direct 3.0V to 3.6V, -40C to +125C, DC to 40 MIPS Connection to the PWM module: 3.0V to 3.6V, -40C to +85C, DC to 50 MIPS - Programmable references with 1024 voltage points Core: 16-Bit dsPIC33F CPU Timers/Output Compare/Input Capture Three General Purpose Timers: Code-Efficient (C and Assembly) Architecture - Three 16-bit and one 32-bit timer/counter Two 40-Bit Wide Accumulators Two Output Compare (OC) modules Single-Cycle (MAC/MPY) with Dual Data Fetch Two Input Capture (IC) modules Single-Cycle Mixed-Sign MUL plus Hardware Divide Peripheral Pin Select (PPS) to allow Function Remap 32-Bit Multiply Support Communication Interfaces Clock Management UART module (12.5 Mbps): 2.0% Internal Oscillator - With support for LIN/J2602 protocols and IrDA Programmable PLLs and Oscillator Clock Sources 4-Wire SPI module Fail-Safe Clock Monitor (FSCM) 2 I C module (up to 1 Mbaud) with SMBus Support Independent Watchdog Timer (WDT) PPS to allow Function Remap Fast Wake-up and Start-up Input/Output Power Management Sink/Source 18 mA on 8 Pins, 10 mA on 10 Pins Low-Power Management modes (Sleep, Idle, Doze) and 6 mA on 17 Pins Integrated Power-on Reset and Brown-out Reset 5V Tolerant Pins Selectable Open-Drain and Pull-ups External Interrupts on up to 30 I/O Pins High-Speed PWM Up to Four PWM Pairs with Independent Timing Qualification and Class B Support Dead Time for Rising and Falling Edges AEC-Q100 REVG (Grade 1, -40C to +125C) 1.04 ns PWM Resolution AEC-Q100 REVG (Grade 0, -40C to +150C) PWM Support for: Class B Safety Library, IEC 60730, VDE Certified - DC/DC, AC/DC, Inverters, PFC and Lighting 6x6x0.5 mm UQFN Package Designed and Programmable Fault Inputs Optimized to ease IPC9592A 2nd Level Temperature Flexible Trigger Configurations for ADC Conversions Cycle Qualification Advanced Analog Features Debugger Development Support ADC module: In-Circuit and In-Application Programming - 10-bit resolution with up to 2 Successive Approximation Two Breakpoints Register (SAR) converters (4 Msps) and up to IEEE 1149.2-Compatible (JTAG) Boundary Scan six Sample-and-Hold (S&H) circuits Trace and Run-Time Watch - Up to 12 input channels grouped into six conversion pairs, plus two voltage reference monitoring inputs - Dedicated result buffer for each analog channel Flexible and Independent ADC Trigger Sources 2008-2014 Microchip Technology Inc. DS70000318G-page 1dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CONTROLLER FAMILIES Remappable Peripherals ADC Device (1) dsPIC33FJ06GS101 18 6 256 8 2 0 1 1 1 2x2 0 3 0 1 1 3 6 13 SOIC dsPIC33FJ06GS102 28 6 256 16 2 0 1 1 1 2x2 0 3 0 1 1 3 6 21 SPDIP, SOIC, QFN-S dsPIC33FJ06GS202 28 6 1K 16 2 1 1 1 1 2x2 2 3 1 1 1 3 6 21 SPDIP, SOIC, QFN-S dsPIC33FJ16GS402 28 16 2K 16 3 2 2 1 1 3x2 0 3 0 1 1 4 8 21 SPDIP, SOIC, QFN-S dsPIC33FJ16GS404 44 16 2K 30 3 2 2 1 1 3x2 0 3 0 1 1 4 8 35 QFN, TQFP, VTLA (1) dsPIC33FJ16GS502 28 16 2K 16 3 2 2 1 1 4x2 43 1 1 2 6 8 21 SPDIP, SOIC, QFN-S, UQFN (1) dsPIC33FJ16GS504 44 16 2K 30 3 2 2 1 1 4x2 4 3 1 1 2 6 12 35 QFN, TQFP, VTLA Note 1: The PWM4H:PWM4L pins are remappable. 2: The PWM Fault pins and PWM synchronization pins are remappable. 3: Only two out of three interrupts are remappable. DS70000318G-page 2 2008-2014 Microchip Technology Inc. Pins Program Flash Memory (Kbytes) RAM (Bytes) Remappable Pins 16-Bit Timer Input Capture Output Compare UART SPI (2) PWM Analog Comparator (3) External Interrupts DAC Output 2 I C SARs Sample-and-Hold (S&H) Circuit Analog-to-Digital Inputs I/O Pins Packages