HV57708 32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs Features HVCMOS technology as driving plasma panels, vacuum uorescent displays, or large matrix LCD displays. 5.0V CMS Logic Output voltage up to +80V The device has 4 parallel 16-bit registers, permitting data Low power level shifting rates 4x the speed of one (they are clocked together). There 32MHz equivalent data rate are also 64 latches and control logic to perform the polarity Latched data outputs select and blanking of the outputs. HV 1 is connected to OUT Foreward and reverse shifting options (DIR pin) the rst stage of the rst shift register through the polarity and blanking logic. Data is shifted through the shift registers Diode to VPP allows efcient power recovery on the logic low to high transition of the clock. The DIR pin Outputs may be hot switched causes CCW shifting when connected to GND, and CW Hi-Rel processing available shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reects the current status of the last bit of the shift register (HV 64). OUT General Description Operation of the shift register is not affected by the LE (latch The HV57708 is a low voltage serial to high voltage enable), BL (blanking), or the POL (polarity) inputs. Transfer parallel converter with push-pull outputs. The device has of data from the shift registers to the latches occurs when been designed for use as a driver for EL displays. It can the LE input is high. The data in the latches is stored when also be used in any application requiring multiple output the LE is low. high voltage current sourcing and sinking capability such Functional Block Diagram O O O O D 1 D 2 D 3 D 4 D I4 D I3 D I2 D I1 V LE BL POL V DD PP HV 1 DIR OUT 5 9 SR1 HV 61 OUT HV 2 OUT 6 10 SR2 HV 62 OUT CLK HV 3 OUT 7 11 SR3 HV 63 OUT HV 4 OUT 8 12 SR4 HV 64 OUT D 4 D 3 D 2 D 1 GND O O O O D I1 D I2 D I3 D I4 Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1 SR2 supplies every fourth output with 2, etc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.comHV57708 Ordering Information Package Options 80-Lead PQFP Device 20.00x14.00mm body 3.40mm height (max) 0.80mm pitch HV57708 HV57708PG-G -G indicates package is RoHS compliant (Green) Pin Conguration Absolute Maximum Ratings Parameter Value Supply voltage, V -0.5V to +7.5V DD Output voltage , V -0.5V to +90V PP Logic input levels -0.3V to V +0.3V DD 80 1 1 Ground current 1.5A 80-Lead PQFP (PG) 2 Continuous total power dissipation 1200mW (top view) Operating temperature range -40C to +85C Product Marking Storage temperature range -65C to +150C Top Marking 3 Lead temperature 260C YYWW YY = Year Sealed HV57708PG Absolute Maximum Ratings are those values beyond which damage to the WW = Week Sealed LLLLLLLLLL device may occur. Functional operation under these conditions is not implied. L = Lot Number Continuous operation of the device at the absolute rating level may affect C = Country of Origin* device reliability. All voltages are referenced to device ground. Bottom Marking A = Assembler ID* Notes: CCCCCCCC = Green Packaging 1. Limited by the total power dissipated in the package. AAA *May be part of top marking 2. For operation above 25C ambient derate linearly to maximum operating temperature at 20mW/C. 80-Lead PQFP (PG) 3. 1.6mm (1/16inch) from case for 10 seconds. Recommended Operating Conditions Sym Parameter Min Max Units V Logic supply voltage 4.5 5.5 V DD V Output voltage 8.0 80 V PP V High-level input voltage V -0.5V - V IH DD V Low-level input voltage 0 0.5 V IL f Clock frequency per register - 8.0 MHz CLK T Operating free-air temperature -40 +85 C A Notes: Power-up sequence should be the following: 1. Apply ground. 2. Apply V . DD 3. Set all inputs (D , CLK, Enable, etc.) to a known state. IN 4. Apply V . PP 5. The V should not drop below V or oat during operation. PP DD Power-down sequence should be the reverse of the above. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2