HV7350DB1 Supertex inc. Eight Channel 60V, 1.0A, Ultrasound Pulser Demoboard General Description This demoboard datasheet describes how to use the The HV7350 is a monolithic eight channel, high-speed, high HV7350DB1 to generate the basic high voltage pulse voltage, ultrasound transmitter RTZ pulser. This integrated, waveform as an ultrasound transmitting pulser. high performance circuit is in a single, 8x8x0.9 mm, 56-lead QFN package. The HV7350 circuit uses DC coupling from a 3.3V logic input to output Tx1~8 internally, therefore the chip needs The HV7350 can deliver a guaranteed 1.0A source and three sets of voltage supply rails: V +3.3V, V +5.0V and sink current to a capacitive transducer with +/-60V peak to LL DD V /V 10 to 60V. The V and V rail voltages can be peak voltage. It is designed for portable medical ultrasound PP NN PP NN changed rather quickly, compared to the capacitor gate- imaging and ultrasound NDT applications. It can also be used coupled driving pulsers. This direct coupling topology of the as a high voltage driver for other piezoelectric or capacitive gate drivers not only saves two high voltage capacitors per MEMS transducers, or for test systems as a signal source or channel, but also makes the PCB layout easier. pulse signal generators. The HV7350DB1 output waveforms can be displayed using The HV7350s circuitry consists of controller logic circuits, an oscilloscope by connecting the scope probe directly to level translators, gate driving buffers and a high current and the test points TX1~8 and GND. The soldering jumper can high voltage MOSFET output stage. The output stages of select whether or not to connect the on-board dummy-load, each channel are designed to provide peak output currents a 330pF capacitor paralleling with a 2.5k resistor. The test typically over 1.0A for pulsing, with up to 60V swings in points can be used to connect the users transducer to easily RTZ mode. The upper limit frequency of the pulser waveform evaluate the pulser. is depending on the load capacitance. Block Diagram +3.3V +3.3V +10 to +60V +3.3V 0.1F11.0F 1.0F .0F 1.0F VLL VDD CPOS CPF VPP 1 of 8 Channels LRP LRP V EXCLK REN REF GND GND VPF RGND +4.0V +5.0V OEN CLK OSC IN HV 1 OUT P-Driver PIN1 40MHz +5.0V EN Waveform NIN1 Logic VPF Generator & TX1 TX1 CPLD DMP Level Translator VNF R2 PIN8 Dummy -5.0V Load NIN8 Rb 6 N-Driver JTAG C4 R3 330pF CLK 2.5k -5V VNF GND GND RTZ RGND RGND WAVE PHAS RGND GND LRN LRN SUB FREQ PWR DAP GND CNEG CNF VNN 1.0F 1.0F OEN PHAS REN OEN 1.0F REN -10 to -60V Doc. DSDB-HV7350DB1 Supertex inc. A070214 www.supertex.comHV7350DB1 Be aware of the parasitic coupling from the outputs to the in- The PCB Layout Techniques put signal terminals of the HV7350. This feedback may cause The large thermal pad at the bottom of the HV7350 package oscillations or spurious waveform shapes on the edges of the is internally connected to the ICs substrate (VSUB). This signal transitions. Since the input operates with signals down thermal pad should be connected to 0V or GND externally on to 3.3V, even small coupling voltages may cause problems. the PCB. Designers need to pay attention to the connecting Use of a solid ground plane and good power and signal layout traces on the outputs TX1~8, specifically the high voltage and practices will prevent this problem. Also ensure that the cir- high speed traces. In particular, controlled impedance to the culating ground return current from a capacitive load cannot ground plane and more trace spacing needs to be applied in react with common inductance to create noise voltages in the this situation. input logic circuitry. High speed PCB trace design practices that are compatible with about 50 to 100MHz operating speeds are used for the Testing the Integrated Pulser demoboard PCB layout. The internal circuitry of the HV7350 The HV7350 pulser demoboard should be powered up with can operate at quite a high frequency, with the primary speed multiple lab DC power supplies with current limiting functions. limitation being load capacitance. Because of this high speed and the high transient currents that result when driving ca- The on-board dummy load 330pF//2.5k should be connect- pacitive loads, the supply voltage bypass capacitors and the ed to the high voltage pulser output through the solder jumper driver to the FETs gate-coupling capacitors should be as when using an oscilloscopes high impedance probe to meet close to the pins as possible. The GND pin should have low the typical loading condition. To evaluate different loading inductance feed-through via connections that are connected conditions, one may change the values of RC within the cur- directly to a solid ground plane. The VDD, VPP, VNN, CPF, rent and power limit of the device. CNF, CNEG and CPOS voltage supply and/or bypass capaci- tor pins can draw fast transient currents of up to 2.0A, so In order to drive the users piezo transducers with a cable, one they should be provided with a low impedance bypass capaci- should match the output load impendence properly to avoid tor at the chips pins. A ceramic capacitor of 1.0 to 2.0F may cable and transducer reflections. A 70 to 75 coaxial cable is be used. Only the VPP and VNN pins to GND capacitors need recommended. The coaxial cable end should be soldered to to be the high-voltage type. The CPF to VPP and CNF to VNN the TX1~8 and GND directly with very short leads. If a users capacitors maybe low voltage. Minimize the trace length to load is being used, the on-board dummy load should be dis- the ground plane, and insert a ferrite bead in the power supply connected by cutting the small shorting copper trace in be- lead to the capacitor to prevent resonance in the power sup- tween the 0 resistors R2, R9, R12, R18, R23, R53, R54 or ply lines. For applications that are sensitive to jitter and noise R55 pads. They are shorted by factory default. and using multiple HV7350 ICs, insert another ferrite bead between each chips supply lines. All the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may Pay particular attention to minimizing trace lengths and us- have limited input voltage. When using the probe on these ing sufficient trace width to reduce inductance. Surface mount high voltage test-points, make sure that V /V voltages do PP NN components are highly recommended. Since the output im- not exceed the probe limit. Using the high impendence oscil- pedance of the HV7350s high voltage power stages is very loscope probe for the on-board test points, it is important to low, in some cases it may be desirable to add a small value have short ground leads to the circuit board ground plane. resistor in series with the output TX1~8 to obtain better wave- form integrity at the load terminals after long cables. This will, If both of the inputs PIN and NIN are high, then the channel of course, reduce the output voltage slew rate at the terminals out TX will be in Hi-Z. of a capacitive load. Doc. DSDB-HV7350DB1 Supertex inc. A070214 2 www.supertex.com