KSZ8462HLI/FHLI IEEE 1588 Precision Time Protocol-Enabled, Two-Port, 10/100 Mbps Ethernet Switch with 8- or 16-Bit Host Interface Advanced Switch Capabilities Features Non-Blocking Store-and-Forward Switch Fabric Management Capabilities Ensures Fast Packet Delivery by Utilizing 1024 The KSZ8462 Includes All the Functions of a 10/ Entry Forwarding Table 100BASE-T/TX/FX Switch System that Combines IEEE 802.1Q VLAN for Up to 16 Groups with Full a Switch Engine, Frame Buffer Management, Range of VLAN IDs Address Look-Up Table, Queue Management, IEEE 802.1p/Q Tag Insertion or Removal on a per MIB Counters, Media Access Controllers (MAC) Port Basis (Egress) and Support Double-Tagging and PHY Transceivers VLAN ID Tag/Untag Options on per Port Basis Non-Blocking Store-and-Forward Switch Fabric Fully Compliant with IEEE 802.3/802.3u Stan- Ensures Fast Packet Delivery by Utilizing 1024 dards Entry Forwarding Table IEEE 802.3x Full-Duplex with Force-Mode Option Port Mirroring/Monitoring/Sniffing: Ingress and/or and Half-Duplex Backpressure Collision Flow Egress Traffic to any Port Control MIB Counters for Fully Compliant Statistics Gath- IEEE 802.1w Rapid Spanning Tree Protocol Sup- ering: 34 Counters per Port port Loopback Modes for Remote Failure Diagnostics IGMP v1/v2/v3 Snooping for Multicast Packet Fil- Rapid Spanning Tree Protocol Support (RSTP) for tering Topology Management and Ring/Linear Recovery QoS/CoS Packets Prioritization Support: 802.1p, Robust PHY Ports DiffServ-Based and Re-Mapping of 802.1p Prior- Two Integrated IEEE 802.3/802.3u-Compliant ity Field per Port Basis on Four Priority Levels Ethernet Transceivers Supporting 10BASE-T and IPv4/IPv6 QoS Support 100BASE-TX IPv6 Multicast Listener Discovery (MLD) Snoop- Copper and 100BASE-FX Fiber Mode Support in ing Support the KSZ8462FHL Programmable Rate Limiting at the Ingress and Copper Mode Support in the KSZ8462HL Egress Ports On-Chip Termination Resistors and Internal Bias- Broadcast Storm Protection ing for Differential Pairs to Reduce Power 1K Entry Forwarding Table with 32K Frame Buffer HP Auto MDI/MDI-X Crossover Support Elimi- Four Priority Queues with Dynamic Packet Map- nates the Need to Differentiate Between Straight ping for IEEE 802.1p, IPv4 TOS (DIFFSERV), or Crossover Cables in Applications IPv6 Traffic Class, etc. MAC Ports Comprehensive Configuration Registers Access Three Internal Media Access Control (MAC) Units Complete Register Access via the Parallel Host 2Kbyte Jumbo Packet Support Interface Tail Tagging Mode (One byte Added before FCS) Facility to Load MAC Address from EEPROM at Support at Port 3 to Inform The Processor Which Power-Up and Reset Time Ingress Port Receives the Packet and its Priority I/O Pin Strapping Facility to Set Certain Register Programmable MAC Addresses for Port 1 and Bits from I/O Pins at Reset Time Port 2 and Source Address Filtering for Imple- Control Registers Configurable On-the-Fly menting Ring Topologies MAC Filtering Function to Filter or Forward IEEE 1588v2 PTP and Clock Synchronization Unknown Unicast Packets Fully Compliant with the IEEE 1588v2 Precision Port 1 and Port 2 MACs Programmable as Either Time Protocol E2E or P2P Transparent Clock (TC) Ports for One-Step or Two-Step Transparent Clock (TC) 1588 Support Timing Corrections E2E (End-to-End) or P2P (Peer-to-Peer) Trans- parent Clock (TC) 2018 Microchip Technology Inc. DS00002641A-page 1KSZ8462HLI/FHLI Grandmaster, Master, Slave, Ordinary Clock (OC) Energy Detect Power-Down (EDPD), which Dis- Support ables the PHY Transceiver when Cables are Removed IEEE1588v2 PTP Multicast and Unicast Frame Support Wake-on-LAN Supported with Configurable Packet Control Transports of PTP Over IPv4/IPv6 UDP and IEEE 802.3 Ethernet Dynamic Clock Tree Control to Reduce Clocking in Areas Not in Use Delay Request-Response and Peer Delay Mech- anism Power Consumption Less than 0.5W Ingress/Egress Packet Time Stamp Capture/ Additional Features Recording and Checksum Update Single 25 MHz 50 ppm Reference Clock Correction Field Update with Residence Time and Requirement Link Delay Comprehensive Programmable Two LED Indica- IEEE1588v2 PTP Packet Filtering Unit to Reduce tors Support for Link, Activity, Full-/Half-Duplex Host Processor Overhead and 10/100 Speed A 64-bit Adjustable System Precision Clock LED Pins Directly Controllable Twelve Trigger Output Units and Twelve Time Industrial Temperature Range: 40C to +85C Stamp Input Units Available for Flexible 64-Pin (10 mm x 10 mm) Lead Free (RoHS) IEEE1588v2 Control of Seven Programmable LQFP Package GPIO 6:0 Pins Synchronized to the Precision Applications Time Clock GPIO Pin Usage for 1 PPS Generation, Fre- Industrial Ethernet Applications that Employ IEEE quency Generator, Control Bit Streams, Event 802.3-Compliant MACs. (Ethernet/IP, Profinet, Monitoring, Precision Pulse Generation, Complex MODBUS TCP, etc) Waveform Generation Real-Time Ethernet Networks Requiring Sub- Host Interface Microsecond Synchronization over Standard Ethernet Selectable 8- or 16-bit Wide Interface IEC 61850 Networks Supporting Power Substa- Supports Big- and Little-Endian Processors tion Automation Indirect Data Bus for Data, Address and Byte Networked Measurement and Control Systems Enable to Access any I/O Registers and RX/TX Industrial Automation and Motion Control Sys- FIFO Buffers tems Large Internal Memory with 12Kbyte for RX FIFO Test and Measurement Equipment and 6Kbytes for TX FIFO Programmable Low, High, and Overrun Water- mark for Flow Control in RX FIFO Efficient Architecture Design with Configurable Host Interrupt Schemes to Minimize Host CPU Overhead and Utilization Queue Management Unit (QMU) Supervises Data Transfers Across This Interface Power and Power Management Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V Integrated Low Voltage (~1.3V) Low-Noise Regu- lator (LDO) Output for Digital and Analog Core Power Supports IEEE P802.3az Energy Efficient Ethernet (EEE) to Reduce Power Consumption in Transceivers in LPI State Full-Chip Hardware or Software Power-Down (All Registers Value are Not Saved and Strap-In Value will Re-Strap After Releasing the Power-Down) DS00002641A-page 2 2018 Microchip Technology Inc.