KSZ8794CNX Integrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface - On-Chip Termination Resistors and Internal Target Applications Biasing for Differential Pairs to Reduce Industrial Ethernet Applications that Employ IEEE Power 802.3-Compliant MACs. (Ethernet/IP, Profinet, - HP Auto MDI/MDI-X Crossover Support Elim- MODBUS TCP, etc.) inates the Need to Differentiate Between VoIP Phone Straight or Crossover Cables in Applications Set-Top/Game Box MAC and GMAC Ports Automotive - Three Internal Media Access Control (MAC1 Industrial Control to MAC3) Units and One Internal Gigabit Media Access Control (GMAC4) Unit IPTV POF SOHO Residential Gateway with Full-Wire Speed - RGMII, MII, or RMII Interfaces Support for the Port 4 GMAC4 with Uplink of Four LAN Ports Broadband Gateway/Firewall/VPN - 2 KByte Jumbo Packet Support - Tail Tagging Mode (One Byte Added Before Integrated DSL/Cable Modem FCS) Support on Port 4 to Inform the Proces- Wireless LAN Access Point + Gateway sor in which Ingress Port Receives the Standalone 10/100 Switch Packet and its Priority Networked Measurement and Control Systems - Supports Reduced Media Independent Inter- face (RMII) with 50 MHz Reference Clock Features Output - Supports Media Independent Interface (MII) Management Capabilities in Either PHY Mode or MAC Mode on Port 4 - The KSZ8794CNX Includes All the Functions - LinkMD Cable Diagnostic Capabilities for of a 10/100BASE-T/TX Switch System Which Combines a Switch Engine, Frame Buffer Determining Cable Opens, Shorts, and Length Management, Address Look-Up Table, Queue Management, MIB Counters, Media Advanced Switch Capabilities Access Controllers (MAC), and PHY Trans- - Non-Blocking Store-and-Forward Switch ceivers Fabric Assures Fast Packet Delivery by Uti- - Non-Blocking Store-and-Forward Switch lizing a 1024-Entries Forwarding Table Fabric Assures Fast Packet Delivery by Uti- - 64 KB Frame Buffer RAM lizing a 1024-Entries Forwarding Table - IEEE 802.1q VLAN Support for up to 128 - Port Mirroring/Monitoring/Sniffing: Ingress Active VLAN Groups (Full-Range 4096 of and/or Egress Traffic to Any Port VLAN IDs) - MIB Counters for Fully Compliant Statistics - IEEE 802.1p/Q Tag Insertion or Removal on Gathering (36 Counters per Port) a Per Port Basis (Egress) - Support Hardware for Port-Based Flush and - VLAN ID Tag/Untag Options on Per Port Freeze Command in MIB Counter. Basis - Multiple Loopback of Remote PHY, and MAC - Fully Compliant with IEEE 802.3/802.3u Modes Support for the Diagnostics Standards - Rapid Spanning Tree Support (RSTP) for - IEEE 802.3x Full-Duplex with Force-Mode Topology Management and Ring/Linear Option and Half-Duplex Back-Pressure Colli- Recovery sion Flow Control Robust PHY Ports - IEEE 802.1w Rapid Spanning Tree Protocol - Four Integrated IEEE 802.3/802.3u-Compli- Support ant Ethernet Transceivers Supporting - IGMP v1/v2/v3 Snooping for Multicast Packet 10BASE-T and 100BASE-TX Filtering - IEEE 802.1az EEE Supported 2016-2021 Microchip Technology Inc. DS00002134C-page 1KSZ8794CNX - QoS/CoS Packets Prioritization Support: tion in Transceivers in LPI State Even 802.1p, DiffServ-Based and Re-Mapping of Though Cables are Not Removed 802.1p Priority Field Per Port Basis on Four - Dynamic Clock Tree Control to Reduce Priority Levels Clocking in Areas that are Not in Use - IPv4/IPv6 QoS Support - Low Power Consumption without Extra - IPv6 Multicast Listener Discovery (MLD) Power Consumption on Transformers Snooping - Voltages: Using External LDO Power Sup- - Programmable Rate Limiting at the Ingress plies and Egress Ports on a Per Port Basis 3.3V or 2.5V - Analog V DDAT - Jitter-Free Per Packet Based Rate Limiting -V Support 3.3V, 2.5V, and 1.8V DDIO Support - Low 1.2V Voltage for Analog and Digital Core - Tail Tag Mode (1 byte Added before FCS) Power Support on Port 4 to Inform the Processor - WoL Support with Configurable Packet Con- which Ingress Port Receives the Packet trol - Broadcast Storm Protection with Percentage Additional Features Control (Global and Per Port Basis) - Single 25 MHz 50 ppm Reference Clock - 1K Entry Forwarding Table with 64 KB Frame Requirement Buffer - Comprehensive Programmable Two-LED - 4 Priority Queues with Dynamic Packet Map- Indicator Support for Link, Activity, Full-/Half- ping for IEEE 802.1P, IPv4 TOS (DIFF- Duplex, and 10/100 Speed SERV), IPv6 Traffic Class, etc. Packaging and Environmental - Supports WoL Using AMDs Magic Packet - Commercial Temperature Range: 0C to - VLAN and Address Filtering +70C - Supports 802.1x Port-Based Security, - Industrial Temperature Range: 40C to Authentication and MAC-Based Authentica- +85C tion via Access Control Lists (ACL) - Small Package Available in a Lead-Free, - Provides Port-Based and Rule-Based ACLs RoHS-Compliant 64-Pin QFN to Support Layer 2 MAC SA/DA Address, - 0.065 m CMOS Technology for Lower Layer 3 IP Address and IP Mask, Layer 4 Power Consumption TCP/UDP Port Number, IP Protocol, TCP Flag and Compensation for the Port Security Filtering - Ingress and Egress Rate Limit Based on Bit per Second (bps) and Packet-Based Rate Limiting (pps) Configuration Registers Access - High-Speed SPI (4-Wire, up to 25 MHz) Inter- face to Access All Internal Registers - MII Management (MIIM, MDC/MDIO 2-Wire) Interface to Access All PHY Registers per Clause 22.2.4.5 of the IEEE 802.3 Specifica- tion - I/O Pin Strapping Facility to Set Certain Reg- ister Bits from I/O Pins During Reset Time - Control Registers Configurable On-the-Fly Power and Power Management - Full-Chip Software Power-Down (All Register Values are Not Saved and Strap-In Value Will Re-Strap After it Releases the Power-Down) - Per-Port Software Power-Down - Energy Detect Power-Down (EDPD), which Disables the PHY Transceiver When Cables are Removed - Supports IEEE P802.3az Energy Efficient Ethernet (EEE) to Reduce Power Consump- 2016-2021 Microchip Technology Inc. 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