KSZ8893FQL Single-Chip 3-Port Switch with Fiber Support Rev. 1.3 General Description The KSZ8893FQL, a highly integrated single-chip 3 port LinkMD Fast Ethernet switch is designed for applications with fiber support such as media converter. It provides two In copper mode, both PHY units support 10Base-T and 10/100 transceivers with patented mixed-signal low- 100Base-TX with HP Auto MDI/MDI-X for reliable power technology, three media access control (MAC) detection of and correction for straight-through and units, a high-speed non-blocking switch fabric, a Layer-2 crossover cables, and LinkMD TDR-based cable managed switch and TS-1000 OAM (Operations, diagnostics for identification of faulty cabling. Administration and Management) V2 in a compact solution. Backwards compatible to the TS-1000 (2002) The high performance switching engine features an specification, TS-1000 V2 is an OAM sub-layer that extensive feature set that includes programmable rate provides communication between CO (central office) and limiting, tag/port-based VLAN, 4 priority class, CPE (customer premises equipment). RMII/MII/SNI and CPU control/data interfaces to effectively address both current and emerging Fast In fiber mode, one PHY unit can be configurable to Ethernet applications. 100Base-FX, 100Base-SX, or 10Base-FL fiber for conversion to 10Base-T and 100Base-TX copper. A fiber The KSZ8893FQL comes in a lead-free package (see LED driver and post amplifier are also included for Ordering Information). 10Base-FL and 100Base-SX applications. Data sheets and support documentation can be found on Micrels web site at: www.micrel.com. Functional Diagram KSZ8893FQL LinkMD is a registered trademark of Micrel, Inc Product/Application names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KSZ8893FQL Control registers configurable on the fly (port-priority, Features 802.1p/d/q, AN) Integrated 3-Port 10/100 Ethernet Switch QoS/CoS Packet Prioritization Support Three MACs and two PHYs fully compliant with IEEE 802.3u standard Per port, 802.1p and DiffServ-based Non-blocking switch fabric assures fast packet Re-mapping of 802.1p priority field per port basis delivery by utilizing an 1K MAC address lookup table Four priority levels and a store-and-forward architecture Advanced Switch Features Full duplex IEEE 802.3x flow control (PAUSE) with force mode option IEEE 802.1q VLAN support for up to 16 groups (full- range of VLAN IDs) Half-duplex back pressure flow control VLAN ID tag/untag options, per port basis HP Auto MDI-X for reliable detection of and correction for straight-through and crossover cables with disable IEEE 802.1p/q tag insertion or removal on a per port and enable option basis (egress) Micrel LinkMD TDR-based cable diagnostics permit Programmable rate limiting at the ingress and egress identification of faulty copper cabling on a per port basis 100Base-FX, 100Base-SX and 10Base-FL fiber Broadcast storm protection with % control (global and support on port 1 per port basis) MII interface supports both MAC mode and PHY mode IEEE 802.1d spanning tree protocol support RMII interface support with external 50MHz system Special tagging mode to inform the processor which clock ingress port receives the packet 7-wire serial network interface (SNI) support for legacy IGMP snooping (Ipv4) and MLD snooping (Ipv6) MAC support for multicast packet filtering Comprehensive LED Indicator support for link, activity, MAC filtering function to forward unknown unicast full/half duplex and 10/100 speed packets to specified port Double-tagging support Fiber Support Low Latency Support Integrated LED driver and post amplifier for 10Base- FL and 100Base-SX optical modules Repeater mode TTC TS-1000 OAM Switch Monitoring Features Supports OAM sub-layer which conforms to TS-1000 Port mirroring/monitoring/sniffing: ingress and/or V2 specification from TTC (Telecommunication egress traffic to any port or MII Technology Committee) MIB counters for fully compliant statistics gathering, 34 Sends and receives OAM frames to Center or MIB counters per port Terminal side Loopback modes for remote diagnostic of failure Loop back mode to support loop back packet from Center side to Terminal side Low Power Dissipation Far-end fault detection with disable and enable Full-chip hardware power-down (register configuration not saved) Link Transparency to indicate link down from link partner Per port based software power-save on PHY (idle link detection, register configuration preserved) Unique User Defined Register (UDR) feature brings OAM to low cost/complexity nodes Voltages: Core 1.2V Comprehensive Configuration Register Access I/O and Transceiver 3.3V 2 SMI, SPI and I C management interfaces to all 8-bit internal registers Available in 128-Pin PQFP, Lead-free package MII management (MIIM) interface to PHY registers I/O pins strapping and EEPROM to program selective registers in unmanaged switch mode 2 M9999-101607-1.3 October 2007