LAN9250/PT Microchip

LAN9250 10/100 Industrial Ethernet Controller & PHY 8/16-Bit Host Bus Interface Highlights - Indexed register or multiplexed bus 16-bit 10/100 industrial Ethernet controller & PHY - 16Kbyte FIFO with flexible TX/RX allocation Interfaces to most 8/16-bit embedded controllers - SPI / Quad SPI support and 32-bit embedded controllers with an 8/16-bit IEEE 1588v2 hardware time stamp unit - Global 64-bit tunable clock bus - Ordinary clock: master / slave, one-step / two-step, end- Integrated Ethernet PHY with HP Auto-MDIX to-end / peer-to-peer delay Integrated Ethernet MAC - Fully programmable timestamp on TX or RX, Compliant with Energy Efficient Ethernet 802.3az timestamp on GPIO Wake on LAN (WoL) support - 64-bit timer comparator event generation (GPIO or IRQ) Integrated IEEE 1588v2 hardware time stamp unit Comprehensive power management features Cable diagnostic support - 3 power-down levels 1.8V to 3.3V variable voltage I/O - Wake on link status change (energy detect) Integrated 1.2V regulator for single 3.3V operation - Magic packet wakeup, Wake on LAN (WoL), wake on Low pin count and small body size package broadcast, wake on perfect DA - Wakeup indicator event signal - Link status change Target Applications Power and I/O Cable, satellite, and IP set-top boxes - Integrated power-on reset circuit Digital televisions & video recorders - Latch-up performance exceeds 150mA per EIA/JESD78, Class II VoIP/Video phone systems - JEDEC Class 3A ESD performance Home gateways - Single 3.3V power supply Test/Measurement equipment (integrated 1.2V regulator) Industrial automation systems Additional Features - Multifunction GPIOs Key Benefits - General purpose timer - Optional EEPROM interface Single-chip Ethernet controller - Ability to use low cost 25MHz crystal for reduced BOM - Fully compliant with IEEE 802.3/802.3u standards Packaging - Integrated Ethernet MAC and PHY - Pb-free RoHS compliant 64-pin QFN or 64-pin TQFP- - 10BASE-T and 100BASE-TX support EP - 100BASE-FX support for external fiber transceiver Available in commercial, industrial, and extended - Automatic polarity detection and correction industrial* temp. ranges (HP Auto-MDIX) *Extended temp. (105C) is supported only in the 64-QFN with an - Full- and Half-duplex support external voltage regulator (internal regulator must be disabled) and - Full-duplex flow control 2.5V (typ) Ethernet magnetics. - Backpressure for half-duplex flow control - Preamble generation and removal - Automatic 32-bit CRC generation and checking - Automatic payload padding and pad removal - Loop-back modes Eliminates dropped packets - Internal buffer memory can store over 200 packets - Automatic PAUSE and back-pressure flow control Flexible address filtering modes - One 48-bit perfect address - 64 hash-filtered multicast addresses - Pass all multicast - Promiscuous mode - Inverse filtering - Pass all incoming with status report - Disable reception of broadcast packets 2015 Microchip Technology Inc. DS00001913A-page 1LAN9250 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: