WWW.Microsemi .COM LX8384 LX8384XX LX8384x-xx TM 5A Low Dropout Positive Regulators PRODUCTION DATA SHEET DESCRIPTION KEY FEATURES available and specified in the Available Three-Terminal Adjustable Or The LX8384/84A/84B Series ICs are Options table below. Fixed Output positive regulators designed to provide 5A The LX8384/84A/84B Series devices are Guaranteed < 1.3V Headroom a output current. These regulators yield pin-compatible with earlier 3-terminal 5A (LX8384A) higher efficiency than currently available regulators, such as the 117 series products, Guaranteed 2.0% Max. devices with all internal circuitry designed but they do require input and output Reference Tolerance (LX8384A) to operate down to a 1V input-to-output capacitors. A minimum 10F capacitor is Guaranteed 1.0% Max. differential. In each of these products, the required on the input and a 15F or greater Reference Tolerance (LX8384B) dropout voltage is fully specified as a on the output of these new devices for 0.015% Line Regulation function of load current. Dropout is stability. Although, these capacitors are 0.15% Load Regulation guaranteed at a maximum of 1.3V (8384A) generally included in most regulator and 1.5V (8384) at maximum output designs. current, decreasing at lower load currents. The LX8384/84A/84B Series quiescent APPLICATIONS In addition, on-chip trimming adjusts the current flows into the load, thereby reference voltage tolerance to 1% maximum Pentium Processor VRE increasing efficiency. This feature contrasts at room temperature and 2% maximum over Application with PNP regulators where up to 10% of the the 0 to 125C range for the LX8384A, High Efficiency Linear output current is wasted as quiescent making this ideal for the Pentium P54C- Regulators current. The LX8384-xxI is specified over VRE specification. The LX8384B offers Power Regulators For Switching the industrial temperature range of -25C to 0.8% tolerance at room temperature and Power Supplies 125C, while the LX8384-xxC/84A- 1.0% maximum over line, load and Battery Chargers xxC/84B-xxC is specified over the temperature. Fixed versions are also Constant Current Regulators commercial range of 0C to 125C. Cyrix 6x86 AMD-K5 IMPORTANT: For the most current data, consult MICROSEMIs website: WWW.Microsemi .COM PACKAGE DATA PACKAGE DATA LX8384x-xx TM 5A Low Dropout Positive Regulators PRODUCTION DATA SHEET ABSOLUTE MAXIMUM RATINGS(NOTE 1) PACKAGE PIN OUT Power Dissipation ................................................................................... Internally Limited TAB is V OUT Input Voltage ................................................................................................................ 10V Input to Output Voltage Differential............................................................................. 10V 3 V Operating Junction Temperature................................................................................150C IN Storage Temperature Range....................................................................... -65C to 150 C 2 V OUT Peak Package Solder Reflow Temp. (40 seconds max. exposure) .................260C (+0,-5) ADJ / 1 GND* Note 1: Exceeding these ratings could cause damage to the device. All voltages are with respect to DD PACKAGE (3-PIN) Ground. Currents are positive into, negative out of specified terminal. (Top View) TAB is V OUT 3 V IN 2 V OUT THERMAL DATA ADJ/ 1 GND DD Plastic TO-263 3-Pin * DT PACKAGE (3-PIN) THERMAL RESISTANCE-JUNCTION TO AMBIENT, 60C/W JA (Top View) THERMAL RESISTANCE-JUNCTION TO TAB, 2.7C/W JT TAB is V OUT Plastic TO-220 3-Pin P 3 V IN THERMAL RESISTANCE-JUNCTION TO AMBIENT, 60C/W JA 2 V OUT 2.7C/W THERMAL RESISTANCE-JUNCTION TO TAB, JT ADJ 1 GND Plastic TO-252 3-Pin DT P PACKAGE (3-PIN) THERMAL RESISTANCE-JUNCTION TO AMBIENT, 60C/W (Top View) JA 2.7C/W THERMAL RESISTANCE-JUNCTION TO TAB, JT *Pin 1 is GND for fixed voltage versions RoHS 100% Matte Tin Lead Finish Junction Temperature Calculation: T = T + (P x ). JT J A D The & numbers are guidelines for the thermal performance of the device/pc-board JA JT system. All of the above assume no ambient airflow. BLOCK DIAGRAM V IN Bias Circuit Thermal Bandgap Control Output Limit Circuit Circuit Circuit Circuit V OUT SOA Protection Circuit ADJ or Current GND* Limit Circuit *Pin 1 is GND for fixed voltage versions Copyright 2000 Microsemi Inc. Page 2 Rev. 2.1f, 2006-01-20 Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570