Revision 13 ProASIC3E Flash Family FPGAs with Optional Soft ARM Support Pro (Professional) I/O Features and Benefits 700 Mbps DDR, LVDS-Capable I/Os High Capacity 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation 600 k to 3 Million System Gates Bank-Selectable I/O Voltagesup to 8 Banks per Chip 108 to 504 kbits of True Dual-Port SRAM Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/ Up to 620 User I/Os 2.5V/1.8V/1.5V, 3.3V PCI / 3.3V PCI-X, and LVCMOS 2.5 V / 5.0 V Input Reprogrammable Flash Technology Differential I/O Standards: LVPECL, LVDS, B-LVDS, and 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS M-LVDS Process Voltage-Referenced I/O Standards: GTL+ 2.5V/3.3V, GTL Instant On Level 0 Support 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Single-Chip Solution Class I and II Retains Programmed Design when Powered Off I/O Registers on Input, Output, and Enable Paths On-Chip User Nonvolatile Memory Hot-Swappable and Cold Sparing I/Os 1 kbit of FlashROM with Synchronous Interfacing Programmable Output Slew Rate and Drive Strength High Performance Programmable Input Delay 350 MHz System Performance Schmitt Trigger Option on Single-Ended Inputs 3.3 V, 66 MHz 64-Bit PCI Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test In-System Programming (ISP) and Security Pin-Compatible Packages across the ProASIC 3E Family ISP Using On-Chip 128-Bit Advanced Encryption Standard Clock Conditioning Circuit (CCC) and PLL (AES) Decryption via JTAG (IEEE 1532compliant) FlashLock Designed to Secure FPGA Contents Six CCC Blocks, Each with an Integrated PLL Configurable Phase-Shift, Multiply/Divide, Delay Capabilities Low Power and External Feedback Core Voltage for Low Power Wide Input Frequency Range (1.5 MHz to 350 MHz) Support for 1.5-V-Only Systems SRAMs and FIFOs Low-Impedance Flash Switches Variable-Aspect-Ratio 4,608-Bit RAM Blocks (1, 2, 4, 9, High-Performance Routing Hierarchy and 18 organizations available) Segmented, Hierarchical Routing and Clock Structure True Dual-Port SRAM (except 18) Ultra-Fast Local and Long-Line Network 24 SRAM and FIFO Configurations with Synchronous Operation Enhanced High-Speed, Very-Long-Line Network up to 350 MHz High-Performance, Low-Skew Global Network ARM Processor Support in ProASIC3E FPGAs Architecture Supports Ultra-High Utilization M1 ProASIC3E DevicesCortex-M1 Soft Processor Available with or without Debug Table 1-1 ProASIC3E Product Family ProASIC3E Devices A3PE600 A3PE1500 A3PE3000 1 Cortex-M1 Devices M1A3PE1500 M1A3PE3000 System Gates 600,000 1,500,000 3,000,000 VersaTiles (D-flip-flops) 13,824 38,400 75,264 RAM Kbits (1,024 bits) 108 270 504 4,608-Bit Blocks 24 60 112 FlashROM Kbits 11 1 Secure (AES) ISP Yes Yes Yes 2 CCCs with Integrated PLLs 66 6 3 VersaNet Globals 18 18 18 I/O Banks 88 8 Maximum User I/Os 270 444 620 Package Pins PQFP PQ208 PQ208 PQ208 FBGA FG256, FG484 FG484, FG676 FG324, FG484, FG896 Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. The PQ208 package supports six CCCs and two PLLs. 3. Six chip (main) and three quadrant global networks are available. 4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs datasheet. January 2013 I 2013 Microsemi CorporationProASIC3E Flash Family FPGAs 1 I/Os Per Package 3 3 ProASIC3E Devices A3PE600 A3PE1500 A3PE3000 2 Cortex-M1 Devices M1A3PE1500 M1A3PE3000 I/O Types Package PQ208 147 65 147 65 147 65 FG256 16579 FG324 221 110 FG484 270 135 280 139 341 168 FG676 444 222 FG896 620 310 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E FPGA Fabric Users Guide to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows: SSTL3(I) and (II): up to 40 I/Os per north or south bank LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). 6. indicates RoHS-compliant packages. Refer to theProASIC3E Ordering Informatio on page III for the location of the in the part number. Table 1-2 ProASIC3E FPGAs Package Sizes Dimensions Package PQ208 FG256 FG324 FG484 FG676 FG896 Length Width (mm mm) 28 28 17 17 19 19 23 23 27 27 31 31 2 Nominal Area (mm ) 784 289 361 529 729 961 Pitch (mm) 0.5 1.0 1.0 1.0 1.0 1.0 Height (mm) 3.40 1.60 1.63 2.23 2.23 2.23 ProASIC3E Device Status ProASIC3E Devices Status M1 ProASIC3E Devices Status A3PE600 Production A3PE1500 Production M1A3PE1500 Production A3PE3000 Production M1A3PE3000 Production II Revision 13 1 Single-Ended I/O Differential I/O Pairs 1 Single-Ended I/O Differential I/O Pairs 1 Single-Ended I/O Differential I/O Pairs