CEC1702 Cryptographic Embedded Controller 3.3V and 1.8V Operation - Fully Operational on Standby Power 2 ACPI Compliant - DMA-driven I C Network Layer Hardware 2 VTR (standby) and VBAT Power Planes -I C Datalink Compatibility Mode - Multi-Master Capable - Low Standby Current in Sleep Mode ARM Cortex -M4 Processor Core - Supports Clock Stretching - 32-Bit ARM v7-M Instruction Set Architecture - Programmable Bus Speed up to 1MHz - Hardware Floating Point Unit (FPU) - Hardware Bus Access Fairness Interface - Single 4GByte Addressing Space (Von Neu- - SMBus Time-outs Interface mann Model) - All Ports Assignable to Any Controller - Little-Endian Byte Ordering - All ports 1.8V-capable - Bit-Banding Feature Included General Purpose Serial Peripheral Interface Con- - NVIC Nested Vectored Interrupt Controller troller - Up to 240 Individually-Vectored Interrupt Sources - One 4-pin Full Duplex Serial Communication Supported Interface - 8 Levels of Priority, Individually Assignable By Vector - Flexible Clock Rates - Chip-Level Interrupt Aggregator supported, to - SPI Burst Capable expand number of interrupt sources or reduce One Quad Serial Peripheral Interface (SPI) Con- number of vectors troller - System Tick Timer - Master Only SPI Controller - Complete ARM-Standard Debug Support - Mappable to two ports (only 1 port active at a - JTAG-Based DAP Port, Comprised of SWJ-DP and time) AHB-AP Debugger Access Functions - Dual and Quad I/O Support - Full DWT Hardware Functionality: 4 Data - Flexible Clock Rates Watchpoints and Execution Monitoring - Full FPB Hardware Breakpoint Functionality: 6 - SPI Burst Capable Execution Breakpoints and 2 Literal (Data) - SPI Controller Operates with Internal DMA Breakpoints Controller with CRC Generation - Comprehensive ARM-Standard Trace Sup- 13 x 8 Interrupt Capable Multiplexed Keyboard port Scan Matrix - Full DWT Hardware Trace Functionality for - Optional Push-Pull Drive for Fast Signal Watchpoint and Performance Monitoring Switching - Full ITM Hardware Trace Functionality for Two Breathing/Blinking LED Interfaces Instrumented Firmware Support and Profiling - Supports three modes of operation: - Full TPIU Functionality for Trace Output - Blinking Mode with Programmable Blink Rates Communication - Breathing LED Output - MPU Feature -8-bit PWM - 1S Delay Register - Breathing LED Supports Piecewise-linear Internal Memory Brightness Curves, Symmetric or Asymmetric - 64k Boot ROM - Supports Low Power Operation in Blinking - Two blocks of SRAM, totaling 480KB and Breathing Modes - Each block can be used for either program or data - Operates on Standby Power - 128 Bytes Battery Powered SRAM - Operates in Chip s System Deepest Sleep State on Battery Backed Resources 32kHz standby clock - Power-Fail Status Register - Operational in EC Sleep State - 32 KHz Clock Generator - Pin buffers capable of sinking up to 12 mA - Week Alarm Timer Interface Two Resistor/Capacitor Identification Detection - Real Time Clock (RC ID) ports - VBAT-Powered Control Interface - Single Pin Interface to External Inexpensive - Two Wake-up Input Signals RC Circuit - Optional Latching of Wake-up Inputs - Replacement for Multiple GPIOs - VBAT-Backed 128 Byte Memory - Provides 8 Quantized States on One Pin 2 Four I C Host Controllers General Purpose I/O Pins - Allows Master or Dual Slave Operation - Up to 65 GPIOs 2018-2019 Microchip Technology Inc. DS00002207E-page 1CEC1702 - Glitch protection on most GPIO pins - 5 Channels -1 Battery-powered General Purpose Outputs - Integral Non-Linearity of 1.5 LSB Differential - All GPIOs can be powered by 1.8V Non-Linearity of 1.0 LSB - Programmable Drive Strength and Slew Rate Two Standard 16C550 UARTs on all GPIOs - Both UARTs with 4-pin Interface Programmable 16-bit Counter/Timer Interface - Programmable Input/output Pin Polarity Inver- - Four 16-bit Auto-reloading Counter/Timer sion Instances - Programmable Main Power or Standby Power - Four Operating Modes per Instance: Timer, Functionality One-shot, Event and Measurement Trace FIFO Debug Port (TFDP) - 3 External Inputs Integrated Standby Power Reset Generator - 2 External Outputs - Reset Input Pin Hibernation Timer Interface Clock Generator - Two 32.768 KHz Driven 16-bit Timers - 32.768KHz Clock Source - Programmable Wake-up from 0.5ms to 128 Minutes - Low power 32KHz crystal oscillator - One 32.768 KHz Driven 32-bit RTOS Timer - Optional use of a crystal-free silicon oscillator with 2% - Programmable Wake-up from 30 S to 35 Hours Accuracy - Auto Reload Option - Optional use of 32.768 KHz input Clock System Watch Dog Timer (WDT) - Operational on Suspend Power Input Capture Timer - Programmable Clock Power Management Con- - 32-bit Free-running timer trol and Distribution - Four 32-bit Capture Registers - 48 MHz PLL - One Compare Timer with Optional Toggling Multi-purpose AES Cryptographic Engine Output - Hardware support for ECB, CTR, CBC and - Capture Interrupts with Programmable Edge OFB AES modes Detection - Support for 128-bit, 192-bit and 256-bit key - Compare Timer and Counter Overflow Inter- length rupts - DMA interface to SRAM, shared with Hash Week Timer engine - Power-up Event Output Cryptographic Hash Engine - Week Alarm Interrupt with 1 Second to 8.5 Year - Support for SHA-1, SHA-256, SHA-512 Time-out - DMA interface to SRAM, shared with AES - Sub-Week Alarm Interrupt with 0.50 Seconds - engine 72.67 hours time-out Public Key Cryptographic Engine - 1 Second and Sub-second Interrupts - Hardware support for RSA and Elliptic Curve Real Time Clock (RTC) public key algorithms - VBAT Powered - RSA keys length from 1024 to 4096 bits - 32KHz Crystal Oscillator - ECC Prime Field and Binary Field keys up to - Time-of-Day and Calendar Registers 640 bits - Programmable Alarms - Microcoded support for standard public key - Supports Leap Year and Daylight Savings Time algorithms Pulse-Width Modulator Support Cryptographic Features - Seven Programmable PWM Outputs - True Random Number Generator - Multiple Clock Rates - 1K bit FIFO - 16-Bit On and 16-Bit Off Counters - Monotonic Counter - Optional Inverted Output Boot ROM Secure Boot Loader FAN Support - Hardware Root of Trust (RoT) using Secure - Two Fan Tachometer Inputs Boot and Immutable Code - Two RPM-Based Fan Speed Controllers - Each includes one Tach input and one PWM output - Supports 2 Code Images in external SPI - 3% accurate from 500 RPM to 16k RPM Flash (Primary and Fallback image) - Automatic Tachometer feedback - Authenticates SPI Flash image before loading - Aging Fan or Invalid Drive Detection - Spin Up Routine - Support AES-256 Encrypted SPI Flash images - Ramp Rate Control Package - RPM-based Fan Speed Control Algorithm - 84 Pin WFBGA RoHS Compliant package ADC Interface - 10-bit Conversion in 1 s DS00002207E-page 2 2018-2019 Microchip Technology Inc.