MCP3202 MCP3202 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Features Description 12-bit resolution The MCP3202 is a successive approximation 12-bit analog-to-digital (A/D) converter with on-board sample 1 LSB maximum DNL and hold circuitry. 1 LSB maximum INL (MCP3202-B) The MCP3202 is programmable to provide a single 2 LSB maximum INL (MCP3202-C) pseudo-differential input pair or dual single-ended Analog inputs programmable as single-ended or inputs. Differential Nonlinearity (DNL) is specified at pseudo-differential pairs 1 LSB, and Integral Nonlinearity (INL) is offered in On-chip sample and hold 1LSB (MCP3202-B) and 2LSB (MCP3202-C) SPI Serial Interface (Modes 0,0 and 1,1) versions. Single supply operation: 2.7V-5.5V Communication with the device is done using a simple 100 ksps maximum sampling rate at V =5V DD serial interface compatible with the SPI protocol. The 50 ksps maximum sampling rate at V =2.7V device is capable of conversion rates of up to 100 ksps DD Low power CMOS technology at 5V and 50 ksps at 2.7V. 500 nA typical standby current, 5 A maximum The MCP3202 operates over a broad voltage range, 2.7V to 5.5V. Low-current design permits operation with 550 A maximum active current at 5V typical standby and active currents of only 500 nA and Industrial temp range: -40C to +85C 375 A, respectively. 8-pin MSOP, PDIP, SOIC and TSSOP packages The MCP3202 is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Applications Sensor Interface Package Types Process Control Data Acquisition PDIP, MSOP, SOIC, TSSOP Battery Operated Systems CS/SHDN 1 8 V /V DD REF Functional Block Diagram CH0 2 7 CLK 6 CH1 3 D OUT V V DD SS V 4 5 D SS IN Input CH0 Channel DAC CH1 Mux Comparator 12-Bit SAR Sample and Hold Shift Register Control Logic CS/SHDN D CLK D IN OUT 1999-2011 Microchip Technology Inc. DS21034F-page 1MCP3202 Notice: Stresses above those listed under Absolute 1.0 ELECTRICAL Maximum Ratings may cause permanent damage to the CHARACTERISTICS device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not Absolute Maximum Ratings implied. Exposure to maximum rating conditions for extended V -V .........................................................................7.0V periods may affect device reliability. DD SS All Inputs and Outputs w.r.t. V ............. -0.6V to V +0.6V SS DD Storage Temperature.....................................-65C to +150C Ambient temperature with power applied.......-65C to +150C Maximum Junction Temperature (T )..........................+150C J ESD Protection On All Pins (HBM) 4kV ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5.5V, V = 0V, DD SS T = -40C to +85C, f = 100 ksps and f = 18*f . A SAMPLE CLK SAMPLE Parameter Sym Min. Typ. Max. Units Conditions Conversion Rate: Conversion Time t 12 clock CONV cycles Analog Input Sample Time t 1.5 clock SAMPLE cycles Throughput Rate f 100 ksps V = V = 5V SAMPL DD REF 50 ksps V = V = 2.7V DD REF DC Accuracy: Resolution 12 bits Integral Nonlinearity INL 0.75 1 LSB MCP3202-B 1 2 LSB MCP3202-C Differential Nonlinearity DNL 0.5 1 LSB No missing codes over temperature Offset Error 1.25 3 LSB Gain Error 1.25 5 LSB Dynamic Performance: Total Harmonic Distortion THD -82 dB V = 0.1V to 4.9V 1 kHz IN Signal-to-Noise and Distortion SINAD 72 dB V = 0.1V to 4.9V 1 kHz IN (SINAD) Spurious Free Dynamic Range SFDR 86 dB V = 0.1V to 4.9V 1 kHz IN Analog Inputs: Input Voltage Range for CH0 or V V V SS DD CH1 in Single-Ended Mode Input Voltage Range for IN+ in IN+ IN- V +IN- See Sections 3.1 and 4.1 DD Pseudo-Differential Mode Input Voltage Range for IN- in IN- V -100 V +100 mV See Sections 3.1 and 4.1 SS SS Pseudo-Differential Mode Leakage Current .001 1 A Switch Resistance R 1k See Figure 4-1 SS Sample Capacitor C 20 pF See Figure 4-1 SAMPLE Digital Input/Output: Data Coding Format Straight Binary High Level Input Voltage V 0.7 V V IH DD Low Level Input Voltage V 0.3 V V IL DD Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 Maintaining Minimum Clock Speed for more information. DS21034F-page 2 1999-2011 Microchip Technology Inc.