MCP37210-200I/TL Microchip

MCP37210-200 MCP37D10-200 200 Msps, 12-Bit Low-Power Single-Channel ADC Digital Signal Post-Processing (DSPP) Options: Features - Decimation filters for improved SNR Sample Rates: 200 Msps - Offset and Gain adjustment Signal-to-Noise Ratio (SNR) with f =15MHz IN - Noise-Shaping Requantizer (NSR) and -1 dBFS: - Digital Down-Conversion (DDC) with I/Q or - 67 dBFS (typical) at 200 Msps f /8 output (MCP37D10-200) S Spurious-Free Dynamic Range (SFDR) with Built-In ADC Linearity Calibration Algorithms: f = 15 MHz and -1 dBFS: IN - Harmonic Distortion Correction (HDC) - 96 dBc (typical) at 200 Msps - DAC Noise Cancellation (DNC) Power Dissipation with LVDS Digital I/O: - Dynamic Element Matching (DEM) - 337 mW at 200 Msps - Flash Error Calibration Power Dissipation with CMOS Digital I/O: Serial Peripheral Interface (SPI) - 304 mW at 200 Msps, output clock = 100 MHz Package Options: Power Dissipation Excluding Digital I/O: - VTLA-124 (9 mm x 9 mm x 0.9 mm) - 256 mW at 200 Msps - TFBGA-121 (8 mm x 8 mm) Power-Saving Modes: No external reference decoupling capacitor - 89 mW during Standby required for TFBGA Package - 24 mW during Shutdown Industrial Temperature Range: -40C to +85C Supply Voltage: - Digital Section: 1.2V, 1.8V Typical Applications - Analog Section: 1.2V, 1.8V Communication Instruments Selectable Full-Scale Input Range: up to 1.8 V P-P Microwave Digital Radio Analog Input Bandwidth: 650 MHz Cellular Base Stations Output Interface: Radar - Parallel CMOS, DDR LVDS Scanners and Low-Power Portable Instruments Output Data Format: Industrial and Consumer Data Acquisition System - Two s complement or offset binary Optional Output Data Randomizer ( ) 1 Device Offering Digital Decimation Digital Noise-Shaping Part Number Sample Rate Resolution (FIR Filters) Down-Conversion Requantizer MCP37210-200 200 Msps 12 Yes No Yes MCP37D10-200 200 Msps 12 Yes Yes Yes MCP37220-200 200 Msps 14 Yes No No MCP37D20-200 200 Msps 14 Yes Yes No Note 1: Devices in the same package type are pin-compatible. 2015-2016 Microchip Technology Inc. DS20005395B-page 1MCP37210-200 AND MCP37D10-200 Functional Block Diagram AV AV GND DV DV DD12 DD18 DD12 DD18 Duty Cycle DLL CLK+ Clock Correction Selection CLK- PLL DCLK+ Output Clock Control DCLK- Digital Signal Post-Processing: A + IN - Decimation Pipelined - Noise-Shaping Requantizer (NSR) ADC - Offset/Gain Adjustment MCP37D10-200: A - IN - Digital Down-Conversion (DDC) OVR V V REF+ REF- WCK Output Control: V - CMOS CM - DDR LVDS Reference Q 11:0 SENSE Generator Internal Registers V BG REF+ REF- SDIO SCLK CS DS20005395B-page 2 2015-2016 Microchip Technology Inc.