Resistor Ladder (R ) LAD MCP6S91/2/3 Single-Ended, Rail-to-Rail I/O, Low-Gain PGA Features Description Multiplexed Inputs: 1 or 2 channels The Microchip Technology Inc. MCP6S91/2/3 are analog Programmable Gain Amplifiers (PGAs). They 8 Gain Selections: can be configured for gains from +1 V/V to +32 V/V and - +1, +2, +4, +5, +8, +10, +16 or +32 V/V the input multiplexer can select one of up to two chan- Serial Peripheral Interface (SPI ) nels through a SPI port. The serial interface can also Rail-to-Rail Input and Output put the PGA into shutdown to conserve power. These Low Gain Error: 1% (max.) PGAs are optimized for high-speed, low offset voltage Offset Mismatch Between Channels: 0 V and single-supply operation with rail-to-rail input and output capability. These specifications support single- High Bandwidth: 1 to 18 MHz (typ.) supply applications needing flexible performance or Low Noise: 10 nV/ Hz 10 kHz (typ.) multiple inputs. Low Supply Current: 1.0 mA (typ.) The one-channel MCP6S91 and the two-channel Single Supply: 2.5V to 5.5V MCP6S92 are available in 8-pin PDIP, SOIC and MSOP Extended Temperature Range: -40C to +125C packages. The two-channel MCP6S93 is available in a 10-pin MSOP package. All parts are fully specified from Typical Applications -40C to +125C. A/D Converter Driver Package Types Multiplexed Analog Applications Data Acquisition MCP6S91 MCP6S93 Industrial Instrumentation PDIP, SOIC, MSOP MSOP Test Equipment V 1 8 V OUT V V DD 1 10 OUT DD SCK Medical Instrumentation CH0 2 7 CH0 2 9 SCK V 3 6 SI REF CH1 3 8 SO Block Diagram V SS 4 5 CS V 4 7SI REF V56 CS V SS DD MCP6S92 PDIP, SOIC, MSOP CH0 V 1 V OUT 8 MUX DD CH1 V OUT CH0 2 SCK 7 CH1 3 CS 6 SI SI SPI V 4 SS 5 CS SO R Logic F SCK 8 Gain Switches R G V V REF SS 2004 Microchip Technology Inc. DS21908A-page 1MCP6S91/2/3 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function V Analog Output OUT Absolute Maximum Ratings CH0, CH1 Analog Inputs V V ........................................................................7.0V DD SS V External Reference Pin REF All inputs and outputs..................... V 0.3VtoV +0.3V SS DD V Negative Power Supply SS Difference Input voltage ....................................... V V DD SS SPI Chip Select CS Output Short Circuit Current ..................................continuous SI SPI Serial Data Input Current at Input Pin .............................................................2mA SO SPI Serial Data Output Current at Output and Supply Pins ................................ 30 mA SCK SPI Clock Input Storage temperature .....................................-65C to +150C Junction temperature ..................................................+150C V Positive Power Supply DD ESD protection on all pins (HBM MM) ................ 4 kV 200V Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25C, V = +2.5V to +5.5V, V = GND, V = V , G = +1 V/V, A DD SS REF SS Input = CH0 = (0.3V)/G, CH1 = 0.3V, R =10k to V /2, SI and SCK are tied low and CS is tied high. L DD Parameters Sym Min Typ Max Units Conditions Amplifier Inputs (CH0, CH1) Input Offset Voltage V -4 +4 mV G = +1 OS Input Offset Voltage Mismatch V 0 V Between inputs (CH0, CH1) OS Input Offset Voltage Drift V / T 1.8 V/CT = -40C to +125C OS A A Power Supply Rejection Ratio PSRR 70 90 dB G = +1 (Note 1) Input Bias Current I 1 pA CHx = V /2 B DD Input Bias Current at I 30 pA CHx = V /2, T = +85C B DD A Temperature I 600 pA CHx = V /2, T = +125C B DD A 13 Input Impedance Z 10 7 pF IN Input Voltage Range V V 0.3 V + 0.3 V (Note 2) IVR SS DD Reference Input (V ) REF Input Impedance Z (5/G) 6 k pF IN REF Voltage Range V V V V (Note 2) IVR REF SS DD Amplifier Gain Nominal Gains G 1 to 32 V/V +1, +2, +4, +5, +8, +10, +16 or +32 DC Gain Error G = +1 g -0.2 +0.2 % V 0.3V to V 0.3V E OUT DD G +2 g -1.0 +1.0 % V 0.3V to V 0.3V E OUT DD DC Gain Drift G = +1 G/ T 0.0002 %/C T = -40C to +125C A A G +2 G/ T 0.0004 %/C T = -40C to +125C A A Note 1: R (R +R in Figure 4-1) connects V , V and the inverting input of the internal amplifier. The MCP6S92 has LAD F G REF OUT V tied internally to V , so V is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is REF SS SS recommended that the MCP6S92s V pin be tied directly to ground to avoid noise problems. SS 2: The MCP6S92s V and V are not tested in production they are set by design and characterization. IVR IVR REF 3: I includes current in R (typically 60 A at V = 0.3V). Both I and I exclude digital switching currents. Q LAD OUT Q Q SHDN 2004 Microchip Technology Inc. DS21908A-page 2