MEC1723N-B0-I/LJ Microchip

MEC172x Keyboard and Embedded Controller for Notebook PC - SPI Master controller Operating Conditions - Supports Mode 0 and mode 3 Operating Voltages: 3.3 V and 1.8 V -24MHz o o C to 85 C Operating Temperature Range: -40 Clocks Low Power Modes 96 MHz Internal PLL Chip is designed to always operate in Lowest 32 kHz Clock Sources Power state during Normal Operation - Internal 32 kHz silicon oscillator Supports all 5 ACPI Power States for PC plat- forms - External 32 kHz crystal (XTAL) source Supports 2 Chip-level Sleep Modes: Light Sleep - External single-ended 32 kHz clock and Heavy Sleep source - Low Standby Current in Sleep Modes Package Options ARM Cortex-M4F Embedded Processor - 144 pin WFBGA Programmable clock frequency up to 48 MHz - 176 pin WFBGA Fixed point processor Security Features Single 4GByte Addressing Space Boot ROM Secure Boot Loader Nested Vectored Interrupt Controller (NVIC) - Hardware Root of Trust (RoT) using Secure - Maskable Interrupt Controller Boot and Immutable code - Maskable hardware wake up events - Supports 2 Code Images in external SPI - 8 Levels of priority, individually assignable by Flash (Primary and Fall back image) vector - Authenticates SPI Flash image before load- EC Interrupt Aggregator expands number of Inter- ing rupt sources supported or reduces number of vec- - Support AES-256 Encrypted SPI Flash tors needed images Standard debug support Complete ARM Hardware Accelerators: - JTAG-Based DAP port, comprised of SWJ- - Multi purpose AES Crypto Engine: DP and AHB-AP debugger access functions - Support for 128-bit - 256-bit key length Memory Components - Supports Battery Authentication applica- tions - 416KB Code/Data SRAM - Digital Signature Algorithm Support - 352KB optimized for code performance - Support for ECDSA and EC KCDSA - 64KB optimized for data performance - Cryptographic Hash Engine - 128 Bytes Battery Powered Storage SRAM - Support for SHA-1, SHA-256 to SHA-512 -4K bits OTP - Public Key Crypto Engine - In circuit programmable - Hardware support for RSA and Elliptic -ROM Curve asymmetric public key algorithms - Contains Boot ROM - RSA keys length of 1024 to 4096 bits - Contains Runtime APIs for built-in func- - ECC Prime Field keys up to 571 bits tions - ECC Binary Field keys up to 571 bits - 128KB of ROM space - Microcoded support for standard public - Internal EEPROM key algorithms - 4Mbit (512KByte) in-chip SPI Serial Flash in - OTP for storing Keys and IDs specific packages (Refer Internal SPI in Table 1-1) - Lockable on 32 B boundaries to prevent read access or write access - SST25PF040C 2021 Microchip Technology Inc. and its subsidiaries DS00003583F-page 1MEC172x - True Random Number Generator - 2 General purpose SPI - 1 Kbit FIFO - 1 Private SPI Interface - JTAG Disabled by default - 1 In-Chip SPI Two General purpose Serial Peripheral Interface System Host interface (SPI) Controllers Enhanced Serial Peripheral Interface (eSPI) - One EC driven Full Duplex Serial Communi- - Intel eSPI Specification compliant cation Interface - eSPI Interface Base Spec, Intel Doc. - Flexible Clock Rates 327432-004, Rev. 1.0. - SPI burst capable - eSPI Compatibility Spec, Intel Doc. 8042 Emulated Keyboard Controller 562633, Rev. 0.6 - 8042 Style Host Interface - Support for Master Attached Flash Sharing - Port 92 Legacy A20M Support (MAFS) - Fast GATEA20 & Fast CPU RESET - Support for Slave Attached Flash Sharing 18 x 8 Interrupt Capable Multiplexed Keyboard (SAFS) Scan Matrix - Supports all four channels: - Optional Push-Pull Drive for Fast Signal - Peripheral Channel Switching - Virtual Wires Channel PECI Interface 3.1 - Out-of-Band (OOB) Tunneled Message - Support Intels low voltage PECI Channel Port 80 BIOS Debug Port - Run-time Flash Access Channel - Two Ports, Assignable to Any eSPI IO - Supports EC Bus Master to Host Memory Address - Supports up to 66 MHz maximum operating - 24-bit Timestamp with Adjustable Timebase frequency - 16-Entry FIFO One Serial Peripheral Interface (SPI) Slave Peripheral Features - Quad SPI (half-duplex) or Single wire (full duplex) support Internal DMA Controller - Mode 0 and Mode3 operation - Hardware or Firmware Flow Control - Programmable wait time for response delay - Firmware Initiated Memory-to-Memory trans- System to EC Message Interface fers - Three Embedded Memory Interfaces - Hardware CRC-32 Generator on Channel 0 - Provides Two Windows to On-Chip SRAM - 16-Hardware DMA Channels support five for Host Access SMBus Master/Slave Controllers, One Quad - Two Register Mailbox Command Interface SPI Controller and Two General purpose SPI Controllers - Mailbox Registers Interface I2C/SMBus Controllers - Thirty-two 8-bit registers - 5 I2C/SMBus controllers - Two Register Mailbox Command Inter- faces - Up to 16 Configurable I2C ports - Two Register SMI Source Interfaces - Full Crossbar switch allows any port to be connected to any controller - Six ACPI Embedded Controller Interfaces - Supports Promiscuous mode of operation - Five EC Interfaces - Fully Operational on Standby Power - One Power Management Interface - Multi-Master Capable One Serial Peripheral Interface (SPI) Master Con- troller - Supports Clock Stretching - Dual and Quad I/O Support - Programmable Bus Speeds - Flexible Clock Rates - 1 MHz Capable - Support for 1.8V and 3.3V slave devices - Supports DMA Network Layer - SPI Burst Capable General Purpose I/O Pins - SPI Controller Operates with Internal DMA - Inputs: Controller with CRC Generation - Asynchronous rising and falling edge - Mappable to the following ports (only 1 port wakeup detection Interrupt High or Low active at a time) Level - 1 shared SPI Interface DS00003583F-page 2 2021 Microchip Technology Inc. and its subsidiaries.