MT8981D
TM
ISO-CMOS ST-BUS Family
Digital Switch
Data Sheet
April 2011
Features
Zarlink ST-BUS compatible
Ordering Information
4-line x 32-channel inputs
MT8981DP1 44 Pin PLCC* Tubes
4-line x 32-channel outputs
MT8981DPR1 44 Pin PLCC* Tape & Reel
128 ports non-blocking switch
MT8981DE1 40 Pin PDIP* Tubes
Single power supply (+5 V)
*Pb Free Matte Tin
Low power consumption: 30 mW Typ.
-40C to +85C
Microprocessor-control interface
Description
Three-state serial outputs
This VLSI ISO-CMOS device is designed for switching
PCM-encoded voice or data, under microprocessor
control, in a modern digital exchange, PBX or Central
Office. It provides simultaneous connections for up to
128 64 kbit/s channels. Each of the four serial inputs
and outputs consist of 32 64 kbit/s channels
multiplexed to form a 2048 kbit/s ST-BUS stream. In
addition, the MT8981 provides microprocessor read
and write access to individual ST-BUS channels.
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.MT8981D Data Sheet
Change Summary
Changes from March 2005 Issue to April 2011 Issue.
Page Item Change
1 Ordering Information Obsolete Leaded packages, only Pb Free packages are
available.
Figure 2 - Pin Connections
Pin Descripton
Pin #
Name Description
40 44
DIP PLCC
12 DTA Data Acknowledgement (Open Drain Output). This is the data
acknowledgement on the microprocessor interface. This pin is pulled low to signal
that the chip has processed the data. A 909 1/4W, resistor is recommended to be
used as a pullup.
2-4 3-5 STi0- ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS
input streams.
STi2
57 STi3 ST-BUS Input 3 (Input). These are the inputs for the 2048 kbit/s ST-BUS input
streams.
6-9 8-11 IC Internal Connections. Must be connected to V .
DD
10 12 V Power Input. Positive Supply.
DD
11 13 F0i Framing 0-Type (Input). This is the input for the frame synchronization pulse for
the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to
reset on the next negative transition of C4i.
2
Zarlink Semiconductor Inc.