MT90812
Integrated Digital Switch (IDX)
Advance Information
Mar 2011
Ordering Information
Features
MT90812AP 68 Pin PLCC Tubes
MT90812AL 64 Pin MQFP Trays
MT90812APR 68 Pin PLCC Tape & Reel
MT90812AP1 68 Pin PLCC* Tubes, Bake & Drypack
192 channel x 192 channel non-blocking
MT90812AL1 64 Pin MQFP* Trays
switching
MT9 0812APR1 68 Pin PLCC* Tape & Reel,
Bake & Drypack
2 local bus streams @ 2Mb/s supports up to 64
*Pb Free Matte Tin
channels -40 to 85 C
In TDM mode, the expansion bus supports up Description
to 128 channels at 8.192 Mb/s
Rate conversion capability between local and
By integrating key functions needed in voice telecom
expansion bus streams
application, the Integrated Digital Switch (IDX)
Integrated conference bridge, supporting 15 provides a solution-on-a-chip for key telephone
systems, PBX applications or CTI designs. Figure 2
parties over 5 bridges
shows a typical conguration.
Integrated PLL
Frequency Shift Keying (FSK) 1200 baud
The MT90812 provides non-blocking timeslot
transmitter, meeting Bell 202 or CCITT V.23
interchange capability for B, C and D channels, up to
standards
a maximum of 192 channels. It offers conference call
32 channel dual tone generator, including 16
capability for 15 parties over a maximum of 5
standard DTMF tones and tone ringer
conference bridges. With its integrated PLL, the
Expansion bus in IDX Link mode, allows the
MT90812 provides the necessary clocks to support
interconnection of up to 4 IDX devices
peripheral devices, such as codecs or
Programmable per channel gain control from +3
interconnected IDX devices. Integrated into the IDX
to -27dB, increments of 1dB for output channels
is the capability to detect supervisory signalling and
Supervisory signalling cadence detection
to generate FSK 1200-baud signals. In addition, an
capability
integrated digital tone generator produces
continuous dual tones, including standard DTMF.
HDLC resource allocator
D-channel buffering of message information
With its programmable gain control, the IDX allows
C-channel access for control and status
users to use codecs without gain control and also
registers
centrally manage conference calls.
Provides both variable and constant delay
modes
To support both small and large switching platforms,
Parallel microprocessor port, compatible to Intel
a built-in expansion Bus allows the interconnection of
and Motorola and National CPUs
up to 4 IDX devices or external components such as
Supports both A-law or u-law operation
digital switches. When 4 IDX devices are
Supports both ST-BUS, GCI and HMVIP
interconnected, the array is capable of switching 256
framing formats
channels (64x4), handling 60 conference parties
(15x4) and generating additional tones including
programmable ones. Other functions are also
Applications
increased in this conguration. The functional block
diagram is shown in Figure 1.
Computer Telephony Integration (CTI)
Key Telephone Systems
An evaluation board, MEB90812, is available
Private Branch Exchange (PBX) Systems
complete with software and a user manual, which
demonstrates the layout of a typical application
board and facilitates the use of the MT90812, and
peripheral devices such as Zarlinks DNIC products.
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MT90812 Advance Information
STi0
Serial
Gain Parallel
STo0
to
Data
Output
STi1 Control to
Parallel
STo1
Memory
Mux Serial
M Converter
Converter
EST1
U EST0
X
Conference
R+
Connect Memory
Ring
Frequency
R-
FSK and Tone
Generation
Energy Detect HDLC
HDLC
Resource
Controller
Allocator
D-channel
TX/RX
Timing
PLL
&
Control
Microprocessor
CPU
Interface
Frame Pulses and Clocks
Figure 1 - Functional Block Diagram
2B+D
2B+D
2B+D
2B+D
C.O.
2B+D
2B+D
Ports
2B+D
Trunks
2B+D
CODEC
Local 2B+D
2B+D
TDM Bus 2B+D
2B+D
2B+D
Ports
. Analog
.
.
Ports
CODEC
Integrated
Digital Switch
- digital switch
- conferencing
MPU Interface
- tone generation
- D-channel
- energy detection
- Chip control
System Expansion bus (TDM)
Figure 2 - System Blocks - Typical Conguration
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