Features
3000 Dhrystone 2.1 MIPS at 1.3 GHz
Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
13 Selectable Core-to-L3 Frequency Divisors
Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
Selectable L3 Interface of 1.8V or 2.5V
P Typical 12.6W at 1 GHz at V = 1.3V; 8.3W at 1 GHz at V = 1.1V, Full Operating
D DD DD
Conditions
Nap, Doze and Sleep Modes for Power Saving
PowerPC 7457
Superscalar (Four Instructions Fetched Per Clock Cycle)
4 GB Direct Addressing Range
52 RISC
Virtual Memory: 4 Hexabytes (2 )
64-bit Data and 36-bit Address Bus Interface
Microprocessor
Integrated L1: 36 KB Instruction and 32 KB Data Cache
Integrated L2: 512 KB
11 Independent Execution Units and Three Register Files
Write-back and Write-through Operations PC7457
f Max = 1 GHz (1.2 GHz to be Confirmed)
INT
f Max = 133 MHz/166 MHz
BUS
Description
The PC7457 is implementations of the PowerPC microprocessor family of reduced
instruction set computer (RISC) microprocessors. This document describes pertinent
electrical and physical characteristics of the PC7457.
The PC7457 is the fourth implementation of the fourth generation (G4) microproces-
sors from Freescale. The PC7457 implements the full PowerPC 32-bit architecture
and is targeted at networking and computing systems applications. The PC7457 con-
sists of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which
support a glueless backside L3 cache through a dedicated high-bandwidth interface.
The core is a high-performance superscalar design supporting a double-precision
floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-
ports the MPX bus interface to main memory and other system resources. The L3
interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private
memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes
may be used as cache; the remaining 2M bytes must be private memory.
Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455
application if the core power supply is 1.3V.
Rev. 5345DHIREL07/06Screening
CBGA Upscreenings Based on Atmel Standards
Full Military Temperature Range (T = -55 C, +125 C),
J
Industrial Temperature Range (T = -40 C, +110 C)
J
HCTE Package for the 7457
G suffix
CBGA 483
Ceramic Ball Grid Array
GH suffix
HITCE 483
Ceramic Ball Grid Array
2
PC7457
5345DHIREL07/06