PIC24FJ128GA310 FAMILY 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and XLP Technology Extreme Low-Power Features: Peripheral Features (Continued): Multiple Power Management Options for Extreme Seven Input Capture modules, each with a Power Reduction: Dedicated 16-Bit Timer -VBAT allows the device to transition to a backup Seven Output Compare/PWM modules, each with a battery for the lowest power consumption with Dedicated 16-Bit Timer RTCC Enhanced Parallel Master/Slave Port (EPMP/EPSP) - Deep Sleep allows near total power-down with the Hardware Real-Time Clock/Calendar (RTCC): ability to wake-up on external triggers - Runs in Deep Sleep and VBAT modes - Sleep and Idle modes selectively shut down Two 3-Wire/4-Wire SPI modules (support 4 Frame peripherals and/or core for substantial power modes) with 8-Level FIFO Buffer reduction and fast wake-up 2 Two I C modules Support Multi-Master/Slave - Doze mode allows CPU to run at a lower clock mode and 7-Bit/10-Bit Addressing speed than peripherals Four UART modules: Alternate Clock modes Allow On-the-Fly Switching to - Support RS-485, RS-232 and LIN/J2602 a Lower Clock Speed for Selective Power Reduction - On-chip hardware encoder/decoder for IrDA Extreme Low-Power Current Consumption for - Auto-wake-up on Auto-Baud Detect Deep Sleep: - 4-level deep FIFO buffer - WDT: 270 nA 3.3V typical Programmable 32-Bit Cyclic Redundancy Check - RTCC: 400 nA 32 kHz, 3.3V typical (CRC) Generator - Deep Sleep current, 40 na, 3.3V typical Digital Signal Modulator Provides On-Chip FSK and PSK Modulation for a Digital Signal Stream Peripheral Features: Configurable Open-Drain Outputs on Digital I/O Pins LCD Display Controller: High-Current Sink/Source (18 mA/18 mA) on All I/O Pins - Up to 60 segments by 8 commons - Internal charge pump and low-power, internal Analog Features: resistor biasing 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter: - Operation in Sleep mode - Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit) Up to Five External Interrupt Sources - Conversion available during Sleep and Idle Peripheral Pin Select (PPS): Allows Independent I/O Three Rail-to-Rail Enhanced Analog Comparators Mapping of Many Peripherals with Programmable Input/Output Configuration Five 16-Bit Timers/Counters with Prescaler: On-Chip Programmable Voltage Reference - Can be paired as 32-bit timers/counters Charge Time Measurement Unit (CTMU): Six-Channel DMA supports All Peripheral modules: - Used for capacitive touch sensing, up to 24 channels - Minimizes CPU overhead and increases data - Time measurement down to 1 ns resolution throughput - CTMU temperature sensing Memory Remappable Peripherals Device PIC24FJ128GA310 100 128K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y PIC24FJ128GA308 80 128K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y PIC24FJ128GA306 64 128K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y PIC24FJ64GA310 100 64K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y PIC24FJ64GA308 80 64K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y PIC24FJ64GA306 64 64K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y 2010-2014 Microchip Technology Inc. DS30009996G-page 1 Pins Flash Program (bytes) Data SRAM (bytes) 16-Bit Timers Capture Input Compare/PWM Output UART w/IrDA SPI 2 I C 10/12-Bit ADC (ch) Comparators CTMU (ch) EPMP/EPSP LCD (pixels) JTAG Deep Sleep w/VBATPIC24FJ128GA310 FAMILY High-Performance CPU: Special Microcontroller Features: Modified Harvard Architecture Operating Voltage Range of 2.0V to 3.6V Up to 16 MIPS Operation 32 MHz Two On-Chip Voltage Regulators (1.8V and 1.2V) for 8 MHz Internal Oscillator: Regular and Extreme Low-Power Operation - 4x PLL option 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical - Multiple clock divide options Flash Data Retention: 20 Years Minimum - Fast start-up Self-Programmable under Software Control 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier Programmable Reference Clock Output 32-Bit by 16-Bit Hardware Divider In-Circuit Serial Programming (ICSP) and In-Circuit Emulation (ICE) via 2 Pins 16 x 16-Bit Working Register Array JTAG Boundary Scan Support C Compiler Optimized Instruction Set Architecture Fail-Safe Clock Monitor Operation: Two Address Generation Units for Separate Read and Write Addressing of Data Memory - Detects clock failure and switches to on-chip, low-power RC oscillator Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Brown-out Reset (BOR) with Operation Below VBOR High/Low-Voltage Detect (HLVD) Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation Standard and Ultra Low-Power Watchdog Timers (ULPW) for Reliable Operation in Standard and Deep Sleep modes DS30009996G-page 2 2010-2014 Microchip Technology Inc.