PIC24FJ128GL306 FAMILY 16-Bit eXtreme Low-Power Microcontrollers with LCD Controller in Low Pin Count Packages High-Performance CPU Functional Safety and Security Peripherals Modified Harvard Architecture Fail-Safe Clock Monitor Operation: 128 Kbytes Flash Memory - Detects clock failure and switches to on-chip, low-power RC oscillator 8 Kbytes SRAM Power-on Reset (POR), Brown-out Reset (BOR) Up to 16 MIPS Operation 32 MHz 17-Bit x 17-Bit Single-Cycle Hardware Power-up Timer (PWRT) and Oscillator Start-up Fractional/Integer Multiplier Timer (OST) 32-Bit by 16-Bit Hardware Divider Programmable High/Low-Voltage Detect (HLVD) 16-Bit x 16-Bit Working Register Array Flexible Watchdog Timer (WDT) with C Compiler Optimized Instruction Set Architecture RC Oscillator for Reliable Operation Two Address Generation Units (AGUs) for Separate Deadman Timer (DMT) for Monitoring Health Read and Write Addressing of Data Memory of Software Programmable 32-Bit Cyclic Redundancy Check LCD Display Controller (CRC) Generator 32x8 with Up to 256 Pixels Flash OTP by ICSP Write Inhibit LCD Charge Pump CodeGuard Security Core-Independent LCD Animation ECC Flash Memory (128 Kbytes) with Fault Operation in Sleep mode Injection: - Single Error Correction (SEC) Analog Features - Double Error Detection (DED) Up to 17-Channel, Software-Selectable, 10/12-Bit Customer OTP Memory Analog-to-Digital Converter: Unique Device Identifier (UDID) - 12-bit, 350K samples/second conversion rate (single Sample-and-Hold) Special Microcontroller Features - 10-bit, 400K samples/second conversion rate Supply Voltage Range of 2.0V to 3.6V (single Sample-and-Hold) Operating Ambient Temperature Range of - Sleep mode operation -40C to +125C - Low-voltage boost for input On-Chip Voltage Regulators (1.8V) for - Band gap reference input feature Low-Power Operation - Core-independent windowed threshold Flash Memory: compare feature - 10,000 erase/write cycle endurance, typical - Auto-scan feature - Data retention: 20 years minimum Three Analog Comparators with Input Multiplexing: - Self-programmable under software control - Programmable reference voltage for comparators - Flash OTP emulation eXtreme Low-Power Features 8 MHz Fast RC Internal Oscillator: - Multiple clock divide options Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power - Fast start-up Reduction and Fast Wake-up 96 MHz PLL Option Doze mode Allows CPU to Run at a Lower Clock Programmable Reference Clock Output Speed than Peripherals In-Circuit Serial Programming (ICSP) and Alternate Clock modes Allow On-the-Fly In-Circuit Emulation (ICE) via Two Pins Switching to a Lower Clock Speed for Selective JTAG Boundary Scan Support Power Reduction Retention Sleep with On-Chip Ultra Low-Power Retention Regulator 2019-2020 Microchip Technology Inc. DS30010198B-page 1PIC24FJ128GL306 FAMILY Four UART modules: Peripheral Features - LIN/J2602 bus support (auto-wake-up, Independent, Low-Power 32 kHz Timer Oscillator Auto-Baud Detect, Break character support) Six-Channel DMA Controller: - RS-232 and RS-485 support - Minimizes CPU overhead and increases data -IrDA mode (hardware encoder/decoder throughput functions) Timer1: 16-Bit Timer/Counter with External Crystal Five External Interrupt Pins Oscillator Timer1 can Provide an A/D Trigger Hardware Real-Time Clock and Calendar (RTCC) Timer2,3,4,5: 16-Bit Timer/Counter can Create Peripheral Pin Select (PPS) allows Independent 32-Bit Timer Timer3 and Timer5 can Provide an I/O Mapping of Many Peripherals A/D Trigger Configurable Interrupt-on-Change on All I/O Pins: Five MCCP modules, Each with a Dedicated - Each pin is independently configurable for 16/32-Bit Timer: rising edge or falling edge change detection - One 6-output MCCP module Reference Clock Output with Programmable - Four 2-output MCCP modules Divider Two Variable Width, Serial Peripheral Interface (SPI) Four Configurable Logic Cell (CLC) Blocks: Ports on All Devices Three Operation modes: - Two inputs and one output, all mappable to - 3-wire SPI (supports all four SPI modes) peripherals or I/O pins - Up to 32-byte deep FIFO buffer - AND/OR/XOR logic and D/JK flip-flop 2 -I S mode functions - Speed up to 25 MHz 2 Two I C Master and Slave w/Address Masking, Qualification PMBus and IPMI Support AEC-Q100 REVG (Grade 1: -40C to +125C) Compliant TABLE 1: PIC24FJ128GL306 FAMILY DEVICES Memory Peripherals Device PIC24FJ128GL306 128K 8K 64 54 32/33 6 17 3 Yes 1/4 5 2 2 4 4 Yes Yes 256 PIC24FJ128GL305 128K 8K 48 39 24/25 6 12 3 Yes 1/4 5 2 2 4 4 Yes Yes 152 PIC24FJ128GL303 128K 8K 36 29 15/16 6 11 3 Yes 1/4 5 2 2 4 4 Yes Yes 80 PIC24FJ128GL302 128K 8K 28 21 13/14 6 9 3 Yes 1/4 5 2 2 4 4 Yes Yes 42 PIC24FJ64GL306 64K 8K 64 54 32/33 6 17 3 Yes 1/4 5 2 2 4 4 Yes Yes 256 PIC24FJ64GL305 64K 8K 48 39 24/25 6 12 3 Yes 1/4 5 2 2 4 4 Yes Yes 152 PIC24FJ64GL303 64K 8K 36 29 15/16 6 11 3 Yes 1/4 5 2 2 4 4 Yes Yes 80 PIC24FJ64GL302 64K 8K 28 21 13/14 6 9 3 Yes 1/4 5 2 2 4 4 Yes Yes 42 DS30010198B-page 2 2019-2020 Microchip Technology Inc. Program (bytes) SRAM (bytes) Pins GPIO Remappable I/O (PPS) (Output/Input) DMA Channels 10/12-Bit A/D Channels Comparators CRC MCCP 6-Output/2-Output 16-Bit Timers 2 I C Variable Width SPI UART w/IrDA CLC RTCC JTAG LCD Pixels