PIC24FJ256GA705 FAMILY 16-Bit General Purpose Microcontrollers with 256-Kbyte Flash and 16-Kbyte RAM in Low Pin Count Packages High-Performance CPU Low-Power Features Modified Harvard Architecture Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Up to 16 MIPS Operation 32 MHz Reduction and Fast Wake-up 8 MHz Fast RC Internal Oscillator: Doze mode allows CPU to Run at a Lower Clock - 96 MHz PLL option Speed than Peripherals - Multiple clock divide options Alternate Clock modes allow On-the-Fly - Fast start-up Switching to a Lower Clock Speed for Selective 17-Bit x 17-Bit Single-Cycle Hardware Power Reduction Fractional/Integer Multiplier 32-Bit by 16-Bit Hardware Divider Special Microcontroller Features 16-Bit x 16-Bit Working Register Array Supply Voltage Range of 2.0V to 3.6V C Compiler Optimized Instruction Set Architecture Dual Voltage Regulators: Two Address Generation Units for Separate Read - 1.8V core regulator and Write Addressing of Data Memory - 1.2V regulator for Retention Sleep mode Six-Channel DMA Controller Operating Ambient Temperature Range of -40C to +85C Analog Features ECC Flash Memory (256 Kbytes): Up to 14-Channel, Software Selectable, - Single Error Correction (SEC) 10/12-Bit Analog-to-Digital Converter: - Double Error Detection (DED) - 12-bit, 200K samples/second conversion rate - 10,000 erase/write cycle endurance, typical (single Sample-and-Hold) - Data retention: 20 years minimum - Sleep mode operation - Self-programmable under software control - Charge pump for operating at lower AVDD 16-Kbyte SRAM - Band gap reference input feature Programmable Reference Clock Output - Windowed threshold compare feature In-Circuit Serial Programming (ICSP) and - Auto-scan feature In-Circuit Emulation (ICE) via 2 Pins Three Analog Comparators with Input Multiplexing: JTAG Boundary Scan Support - Programmable reference voltage for Fail-Safe Clock Monitor Operation: comparators - Detects clock failure and switches to on-chip, LVD Interrupt Above/Below Programmable Low-Power RC (LPRC) Oscillator VLVD Level Power-on Reset (POR), Brown-out Reset (BOR) Charge Time Measurement Unit (CTMU): and Oscillator Start-up Timer (OST) - Allows measurement of capacitance and time Programmable Low-Voltage Detect (LVD) - Operational in Sleep Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation 2016-2018 Microchip Technology Inc. DS30010118C-page 1PIC24FJ256GA705 FAMILY 2 Two I C Master and Slave w/Address Masking, Peripheral Features and IPMI Support High-Current Sink/Source 18 mA/18 mA on Two UART modules: All I/O Pins - LIN/J2602 bus support (auto-wake-up, Independent, Low-Power 32 kHz Timer Oscillator Auto-Baud Detect (ABD), Break character support) Timer1: 16-Bit Timer/Counter with External Crystal - RS-232 and RS-485 support Oscillator Timer1 can Provide an A/D Trigger -IrDA mode (hardware encoder/decoder Timer2,3: 16-Bit Timer/Counter, can Create 32-Bit functions) Timer Timer3 can Provide an A/D Trigger Five External Interrupt Pins Three Input Capture modules, Each with a Parallel Master Port/Enhanced Parallel Slave Port 16-Bit Timer (PMP/EPSP), 8-Bit Data with External Three Output Compare/PWM modules, Each with Programmable Control (polarity and protocol) a 16-Bit Timer Enhanced CRC module Four MCCP modules, Each with a Dedicated Reference Clock Output with Programmable 16/32-Bit Timer: Divider - One 6-output MCCP module Two Configurable Logic Cell (CLC) Blocks: - Three 2-output MCCP modules - Two inputs and one output, all mappable to Three Variable Width, Synchronous Peripheral peripherals or I/O pins Interface (SPI) Ports on All Devices 3 Operation - AND/OR/XOR logic and D/JK flip-flop modes: functions - 3-wire SPI (supports all 4 SPI modes) Peripheral Pin Select (PPS) with Independent I/O - 8 by 16-bit or 8 by 8-bit FIFO Mapping of Many Peripherals 2 -I S mode TABLE 1: PIC24FJ256GA705 FAMILY DEVICES Memory Peripherals Device PIC24FJ64GA705 64K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes PIC24FJ128GA705 128K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes PIC24FJ256GA705 256K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes PIC24FJ64GA704 64K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes PIC24FJ128GA704 128K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes PIC24FJ256GA704 256K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes PIC24FJ64GA702 64K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes PIC24FJ128GA702 128K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes PIC24FJ256GA702 256K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes DS30010118C-page 2 2016-2018 Microchip Technology Inc. Program (bytes) SRAM (bytes) Pins GPIO DMA Channels 10/12-Bit A/D Channels Comparators CRC MCCP 6-Output/2-Output IC/OC/PWM 16-Bit Timers 2 I C Variable Width SPI LIN-USART/IrDA CTMU Channels EPMP (Address/Data Line) CLC RTCC JTAG