PIC24FJ256GA412/GB412 FAMILY 16-Bit Flash Microcontrollers with Dual Partition Flash Memory, XLP, LCD, Cryptographic Engine and USB On-The-Go Extreme Low-Power Features Dual Partition Flash with Live Update Capability Multiple Power Management Options for Extreme Power Reduction: Capable of Holding Two Independent Software Applications, BAT allows for lowest power consumption on backup -V including Bootloader battery (with or without RTCC) Permits Simultaneous Programming of One Partition while - Deep Sleep allows near total power-down with the ability to Executing Application Code from the Other wake-up on external triggers Allows Run-Time Switching Between Active Partitions - Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake-up Universal Serial Bus Features - Doze mode allows CPU to run at a lower clock speed than (PIC24FJXXXGB4XX Only) peripherals Alternate Clock modes allow On-the-Fly Switching to a Lower USB v2.0 On-The-Go (OTG) Compliant Clock Speed for Selective Power Reduction Dual Role Capable Can Act as Either Host or Peripheral Extreme Low-Power Current Consumption for Deep Sleep: Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB - WDT: 650 nA 2V typical Operation in Host mode - RTCC: 650 nA 32 kHz, 2V typical Full-Speed USB Operation in Device mode - Deep Sleep current, 60 nA typical High-Precision PLL for USB 160 A/MHz in Run mode USB Device mode Operation from FRC Oscillator No Crystal Oscillator Required High-Performance CPU Supports up to 32 Endpoints (16 bidirectional): Modified Harvard Architecture - USB module can use any RAM locations on the device as Up to 16 MIPS Operation 32 MHz USB endpoint buffers 8 MHz Internal Oscillator: On-Chip USB Transceiver with Interface for Off-Chip - 96 MHz PLL option USB Transceiver - Multiple clock divide options Supports Control, Interrupt, Isochronous and Bulk Transfers - Run-time self-calibration capability for maintaining better On-Chip Pull-up and Pull-Down Resistors than 0.20% accuracy - Fast start-up Special Microcontroller Features 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier 32-Bit by 16-Bit Hardware Divider 20,000 Erase/Write Cycle Endurance, Typical 16 x 16-Bit Working Register Array Data Retention: 20 Years Minimum C Compiler Optimized Instruction Set Architecture Self-Programmable under Software Control Two Address Generation Units for Separate Read and Write Supply Voltage Range of 2.0V to 3.6V Addressing of Data Memory Two On-Chip Voltage Regulators (1.8V and 1.2V) for Regular and Extreme Low-Power Operation Cryptographic Engine Programmable Reference Clock Output Performs NIST Standard Encryption/Decryption In-Circuit Serial Programming (ICSP) and Operations without CPU Intervention In-Circuit Emulation (ICE) via 2 Pins AES Cipher Support for 128, 192 and 256-Bit Keys JTAG Boundary Scan Support DES/3DES Cipher Support, with up to Three Unique Keys Fail-Safe Clock Monitor (FSCM) Operation: for 3DES - Detects clock failure and switches to on-chip, Supports ECB, CBC, OFB, CTR and CFB128 modes Low-Power RC (LPRC) Oscillator Programmatically Secure OTP Array for Key Storage Power-on Reset (POR), Power-up Timer (PWRT) True Random Number Generation and Oscillator Start-up Timer (OST) Battery-Backed RAM Key Storage Separate Brown-out Reset (BOR) and Deep Sleep Brown-out Reset (DSBOR) Circuits Analog Features Programmable High/Low-Voltage Detect (HLVD) 10/12-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter: Flexible Watchdog Timer (WDT) with its Own - Conversion rate of 500 ksps (10-bit), 200 kbps (12-bit) RC Oscillator for Reliable Operation - Auto-scan and threshold compare features Standard and Ultra Low-Power Watchdog Timers (ULPW) for - Conversion available during Sleep Reliable Operation in Standard and Deep Sleep modes One 10-Bit Digital-to-Analog Converter (DAC): Temperature Range: -40C to +85C - 1 Msps update rate Three Rail-to-Rail, Enhanced Analog Comparators with Programmable Input/Output Configuration Charge Time Measurement Unit (CTMU): - Used for capacitive touch sensing, up to 24 channels - Time measurement down to 100 ps resolution 2015-2016 Microchip Technology Inc. DS30010089D-page 1PIC24FJ256GA412/GB412 FAMILY Memory Analog Peripherals Digital Peripherals Device PIC24FJ256GA412 256K 16K 121 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 512 Y PIC24FJ256GA410 256K 16K 100 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 480 Y PIC24FJ256GA406 256K 16K 64 16 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 248 Y PIC24FJ128GA412 128K 16K 121 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 512 Y PIC24FJ128GA410 128K 16K 100 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 480 Y PIC24FJ128GA406 128K 16K 64 16 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 248 Y PIC24FJ64GA412 64K 8K 121 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 512 Y PIC24FJ64GA410 64K 8K 100 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 480 Y PIC24FJ64GA406 64K 8K 64 16 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 N Y 248 Y PIC24FJ256GB412 256K 16K 121 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 512 Y PIC24FJ256GB410 256K 16K 100 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 480 Y PIC24FJ256GB406 256K 16K 64 16 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 240 Y PIC24FJ128GB412 128K 16K 121 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 512 Y PIC24FJ128GB410 128K 16K 100 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 480 Y PIC24FJ128GB406 128K 16K 64 16 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 240 Y PIC24FJ64GB412 64K 8K 121 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 512 Y PIC24FJ64GB410 64K 8K 100 24 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 480 Y PIC24FJ64GB406 64K 8K 64 16 1 3 Y 1/6 31/15 6/6 3 4 6 Y 4 Y Y 240 Y Enhanced Parallel Master/Slave Port (EPMP/EPSP) Peripheral Features Hardware Real-Time Clock/Calendar (RTCC) with LCD Display Controller: Timestamping: - Up to 64 Segments by 8 Commons - Tamper detection with timestamping feature and - Internal charge pump and low-power, internal resistor biasing tamper pin - Operation in Sleep mode - Runs in Deep Sleep and VBAT modes Up to Five External Interrupt Sources Four 3-Wire/4-Wire SPI modules (support 4 Frame modes) Peripheral Pin Select (PPS) allows Independent with 8-Level FIFO Buffer I/O Mapping of Many Peripherals 2 Three I C modules support Multi-Master/Slave mode and Six-Channel DMA Supports All Peripheral modules: 7-Bit/10-Bit Addressing - Minimizes CPU overhead and increases Six UART modules: data throughput - Support RS-485, RS-232 and LIN/J2602 Five 16-Bit Timers/Counters with Prescalers: - On-chip hardware encoder/decoder for IrDA - Can be paired as 32-bit timers/counters - Auto-wake-up on Auto-Baud Detect (ABD) Using a combination of Timer, CCP, IC and OC Timers, the - 4-level deep FIFO buffer Device can be Configured to use up to 31 16-Bit Timers, Programmable 32-Bit Cyclic Redundancy Check (CRC) and up to 15 32-Bit Timers Generator Six Input Capture modules, each with a Dedicated Four Configurable Logic Cells (CLCs): 16-Bit Timer - Two inputs and one output, all mappable to Six Output Compare/PWM modules, each with a peripherals or I/O pins Dedicated 16-Bit Timer - AND/OR/XOR logic and D/JK flip-flop functions Six Single Output CCPs (SCCP) and One Multiple High-Current Sink/Source (18 mA/18 mA) on All I/O Pins Output CCP (MCCP) modules: Configurable Open-Drain Outputs on Digital I/O Pins - Independent 16/32-bit time base for each module 5.5V Tolerant Inputs on Multiple I/O Pins - Internal time base and Period registers - Legacy PIC24F Capture and Compare modes (16 and 32-bit) - Special variable frequency pulse and Brushless DC Motor (BDCM) Output modes DS30010089D-page 2 2015-2016 Microchip Technology Inc. Program (bytes) Data (bytes) Pins 10/12-Bit A/D (ch) 10-Bit DAC Comparators CTMU MCCP/SCCP 16/32-Bit Timers IC/OC-PWM 2 I C SPI UART/IrDA EPMP/EPSP CLC USB OTG Crypto Engine LCD Controller (pixels) Deep Sleep + VBAT