PIC24FJ64GA004 FAMILY 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers High-Performance CPU Analog Features Modified Harvard Architecture 10-Bit, up to 13-Channel Analog-to-Digital Converter: Up to 16 MIPS Operation 32 MHz - 500 ksps conversion rate 8 MHz Internal Oscillator with 4x PLL Option and - Conversion available during Sleep and Idle Multiple Divide Options Dual Analog Comparators with Programmable 17-Bit by 17-Bit Single-Cycle Hardware Multiplier Input/Output Configuration 32-Bit by 16-Bit Hardware Divider Peripheral Features 16-Bit x 16-Bit Working Register Array Peripheral Pin Select (PPS): C Compiler Optimized Instruction Set Architecture: - Allows independent I/O mapping of many peripherals - 76 base instructions - Up to 26 available pins (44-pin devices) - Flexible addressing modes - Continuous hardware integrity checking and safety Two Address Generation Units (AGUs) for Separate interlocks prevent unintentional configuration changes Read and Write Addressing of Data Memory 8-Bit Parallel Master/Slave Port (PMP/PSP): Special Microcontroller Features - Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices Operating Voltage Range of 2.0V to 3.6V - Programmable polarity on control lines 5.5V Tolerant Input (digital pins only) Hardware Real-Time Clock/Calendar (RTCC): High-Current Sink/Source (18 mA/18 mA) on All I/O Pins - Provides clock, calendar and alarm functions Flash Program Memory: Programmable Cyclic Redundancy Check (CRC) - 10,000 erase/write Two 3-Wire/4-Wire SPI modules (support 4 Frame - 20-year data retention minimum modes) with 8-Level FIFO Buffer Power Management modes: 2 Two I C modules Support Multi-Master/Slave - Sleep, Idle, Doze and Alternate Clock modes mode and 7-Bit/10-Bit Addressing - Operating current: 650 A/MIPS, typical at 2.0V Two UART modules: - Sleep current: 150 nA, typical at 2.0V - Supports RS-485, RS-232, and LIN/J2602 Fail-Safe Clock Monitor (FSCM) Operation: - On-chip hardware encoder/decoder for IrDA - Detects clock failure and switches to on-chip, - Auto-wake-up on Start bit low-power RC oscillator - Auto-Baud Detect On-Chip, 2.5V Regulator with Tracking mode - 4-level deep FIFO buffer Power-on Reset (POR), Power-up Timer (PWRT) Five 16-Bit Timers/Counters with Programmable Prescaler and Oscillator Start-up Timer (OST) Five 16-Bit Capture Inputs Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation Five 16-Bit Compare/PWM Outputs In-Circuit Serial Programming (ICSP) and Configurable Open-Drain Outputs on Digital I/O Pins In-Circuit Debug (ICD) via 2 Pins Up to 3 External Interrupt Sources JTAG Boundary Scan Support Remappable Peripherals Device PIC24FJ16GA002 28 16K 4K 16 5 5 5 2 2 2 10 2 Y Y PIC24FJ32GA002 28 32K 8K 16 5 5 5 2 2 2 10 2 Y Y PIC24FJ48GA002 28 48K 8K 16 5 5 5 2 2 2 10 2 Y Y PIC24FJ64GA002 28 64K 8K 16 5 5 5 2 2 2 10 2 Y Y PIC24FJ16GA004 44 16K 4K 26 5 5 5 2 2 2 13 2 Y Y PIC24FJ32GA004 44 32K 8K 26 5 5 5 2 2 2 13 2 Y Y PIC24FJ48GA004 44 48K 8K 26 5 5 5 2 2 2 13 2 Y Y PIC24FJ64GA004 44 64K 8K 26 5 5 5 2 2 2 13 2 Y Y 2010-2013 Microchip Technology Inc. DS39881E-page 1 Pins Program Memory (bytes) SRAM (bytes) Remappable Pins Timers 16-Bit Capture Input Compare/ PWM Output UART w/ IrDA SPI 2 I C 10-Bit A/D (ch) Comparators PMP/PSP JTAGPIC24FJ64GA004 FAMILY Pin Diagrams 28-Pin SPDIP, SSOP, SOIC 1 28 MCLR VDD 2 27 AN0/VREF+/CN2/RA0 VSS AN1/VREF-/CN3/RA1 3 26 AN9/RP15/CN11/PMCS1/RB15 4 25 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 5 24 AN11/RP13/CN13/PMRD/RB13 AN4/C1IN-/SDA2/RP2/CN6/RB2 6 23 AN12/RP12/CN14/PMD0/RB12 AN5/C1IN+/SCL2/RP3/CN7/RB3 7 22 PGEC2/TMS/RP11/CN15/PMD1/RB11 VSS 8 21 PGED2/TDI/RP10/CN16/PMD2/RB10 9 20 OSCI/CLKI/CN30/RA2 VCAP/VDDCORE OSCO/CLKO/CN29/PMA0/RA3 10 19 DISVREG 11 18 SOSCI/RP4/PMBE/CN1/RB4 TDO/SDA1/RP9/CN21/PMD3/RB9 SOSCO/T1CK/CN0/PMA1/RA4 12 17 TCK/SCL1/RP8/CN22/PMD4/RB8 VDD 13 16 RP7/INT0/CN23/PMD5/RB7 PGED3/ASDA1/RP5/CN27/PMD7/RB5 14 15 PGEC3/ASCL1/RP6/CN24/PMD6/RB6 (1) 28-Pin QFN 2827 2625242322 PGED1/AN2/C2IN-/RP0/CN4/RB0 1 21 AN11/RP13/CN13/PMRD/RB13 PGEC1/AN3/C2IN+/RP1/CN5/RB1 2 AN12/RP12/CN14/PMD0/RB12 20 AN4/C1IN-/SDA2/RP2/CN6/RB2 3 19 PGEC2/TMS/RP11/CN15/PMD1/RB11 AN5/C1IN+/SCL2/RP3/CN7/RB3 PIC24FJXXGA002 4 18 PGED2/TDI/RP10/CN16/PMD2/RB10 VSS 5 17 VCAP/VDDCORE OSCI/CLKI/CN30/RA2 6 DISVREG 16 OSCO/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9/CN21/PMD3/RB9 8 9 10 11 12 13 14 Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Note 1: Back pad on QFN devices should be connected to Vss. DS39881E-page 2 2010-2013 Microchip Technology Inc. SOSCI/RP4/PMBE/CN1/RB4 AN1/VREF-/CN3/RA1 SOSCO/T1CK/CN0/PMA1/RA4 AN0/VREF+/CN2/RA0 VDD MCLR PIC24FJXXGA002 PGED3/ASDA1/RP5/CN27/PMD7/RB5 VDD PGEC3/ASCL1/RP6/CN24/PMD6/RB6 VSS RP7/INT0/CN23/PMD5/RB7 AN9/RP15/CN11/PMCS1/RB15 TCK/SCL1/RP8/CN22/PMD4/RB8 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14