PL 502-3x PL502-35/-37/-38/-39 750kHz 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise ICs FEATURES PIN CONFIGURATION (Top View) Selectable 750kHz to 800MHz range Low phase noise output ( 10kHz frequency off- 1 VDD 1 SEL0 6 set, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 1 XIN 2 SEL1 5 155.52MHz, -115dBc/Hz for 622.08MHz) 1 XOUT 3 GND 4 LVCMOS (PL502-37), LVPECL (PL502-35 and 1 SEL3 4 CLKC PL502-38) or LVDS (PL502-39) output 3 1 SEL2 5 VDD 12MHz to 25MHz crystal input 2 1 OE 6 CLKT No external load capacitor or varicap required. 1 1 Output Enable selector VCON 7 GND 0 Wide pull range (200 ppm) GND 8 9 GND Selectable /16 to x32 frequency divider/multiplier TSSOP-16L 3.3V operation : Internal pull-up *: On 3x3 package, PL502-35/-38 do not have SEL0 available: Pin 10 Available in 16-Pin TSSOP or 16-pin 3x3mm QFN is VDD, pin 11 is GND. However, PL502-37/-39 have SEL0 (pin 10), GREEN/RoHS compliant packages and pin11 is VDD. See pin assignment table for details. DESCRIPTION The PL502-35 (LVPECL with inverted OE), PL502-37 (LVCMOS), PL502-38 (LVPECL), and PL502-39 (LVDS) are high performance and low phase noise 12 11 10 9 VCXO IC chips. They provide phase noise perfor- XOUT 13 8 GND mance as low as 125dBc at 10kHz offset (at 14 7 SEL3 CLKC PL502-3x 155MHz), by multiplying the input crystal frequency up 15 VDD SEL2 6 to 32x. The wide pull range (200 ppm) and very low 16 5 CLKT OE 1 2 3 4 jitter make them ideal for a wide range of applications, including SONET/SDH and FEC. They accept funda- mental parallel resonant mode crystals from 12MHz to 25MHz. QFN-16L OUTPUT ENABLE LOGICAL LEVELS BLOCK DIAGRAM Part OE State SEL 3:0 0 (Default) Output enabled PL502-38 1 Tri-state OE PLL PL502-35 0 Tri-state CLKC Oscillator (Phase VCON PL502-37 Amplifier Locked 1 (Default) Output enabled CLKT PL502-39 w/ Loop) XIN OE input: Logical states defined by LVPECL levels for PL502-38 integrated Logical states defined by LVCMOS levels for PL502-37/-39 varicaps XOUT PLL by-pass PL502-3x Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 4/15/13 Page 1 XIN VCON GND VDD / GND* GND SEL0 / VDD* GND SEL1 PL502-35/-37/-38/-39 750kHz 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise ICs FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier 0 0 1 1 Fin x 32 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication Note: SEL0 is not available (always 1) for PL502-35 and PL502-38 in 3x3mm package PIN DESCRIPTIONS PL502-35 and PL502-38 (see next page for PL502-37/-39) TSSOP 3x3mm QFN Name Type Description Pin number Pin number XIN 2 12 I Crystal input (See Crystal Specification on page 4) XOUT 3 13 I Crystal output (See Crystal Specification on page 4) OE 6 16 I Output enable pin (See OE logic state table on page 1) VCON 7 1 I Voltage Control input GND 8,9,10,14 2,3,4,8,11 P Ground connection CLKT 11 5 O LVPECL True output CLKC 13 7 O LVPECL Complementary output SEL0 16 Not available I Multiplier selector pins. These pins have an internal pull- SEL1 15 9 I up that will default SEL to 1 when not connected to SEL2 5 15 I GND. SEL3 4 14 I VDD 1, 12 6,10 P +3.3V power supply. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 4/15/13 Page 2