PM5377 TSE 240 Released Single Chip 96-Port STS-1/STM-0 Cross-Connect Each DM block allocated as DMI FEATURES DELAY MANAGEMENT supports arbitrary frame alignment of Provides a 108 byte FIFO for each Implements a 240G memory switch an STS-48 ingress signal to the frame ingress port to support 102 byte fabric with STS-1/AU-3 switching alignment of the synchronous maximum skew among the input links granularity. switching core. (1312 ns for 622 Mbit/s links and 328 96 ingress and 96 egress STS- Each DM block allocated as DMO ns for 2.488 Gbit/s links). 48/STS-12 ports for a maximum of supports alignment of a switch core Provides 13 delay management (DM) 4608 STS-1/AU-3 streams in a single output to a user defined frame blocks that can be allocated to a device. alignment. subset of devices ports (1 through 25) Supports a single-stage, anycast Provides a software configurable delay as either input delay management switching capacity of 240G. register to compensate for differences (DMI) or output delay management in frame boundary arrival times for SWITCH PORT CONFIGURATION (DMO). Each DM block processes a ingress ports without DMI allocated. STS-48 signal for an aggregate delay Each port can be individually Provides 25 software configurable management capacity of 32.5 Gbit/s. configured for 2.488Gbit/s or 622Mbit/s delay registers for ingress ports one Supports ganging of 4 DM blocks to operation. Ingress and egress links of through 25 to allow arbitrary alignment form a delay management group a port can be individually configured. of ingress frames to the device frame (DMG) capable of processing a STS- Optionally inserts AIS on ingress links timing when DMI is allocated to an 192 signal. that are out-of-frame. ingress port. Supports unequipped overwrite, and path AIS overwrite on a per egress port and per egress grain basis. Implements the ESSI Frame layer TOH PROCESSING AND TESTING Supports transport overhead BLOCK DIAGRAM processing of ports in groups of 24. TOH extract clock and data interface LB ID 4:1 1:0 LB ED 4:1 1:0 LB IFP 4:1 capable of extracting a set of TOH LB EFP 4:1 LBTO (x4) LBTE (x4) LB ICLK 4:1 bytes per ingress port. Selection of the LB ECLK 4:1 bytes to be extracted is user programmable on a per 24-port group basis. RASIO RASIO R P/N 1..25 T P/N 1..25 3G ESSI Rx DMI DMO ESSI Tx 3G TOH insert clock and data interface Rx Tx capable of overwriting a set of TOH Memory RASIO RASIO R P/N 26 T P/N 26 bytes per egress port. Selection of the 3G ESSI Rx Switch ESSI Tx 3G Rx Tx bytes to overwrite is user Core programmable on a per 24-port group RASIO RASIO R P/N 27..96 T P/N 27...96 3G ESSI Rx ESSI Tx 3G basis. Rx Tx GLOBAL FRAME RJ0FP CORE J0FP SYNCHRONIZATION Supports frame synchronization via a global frame pulse input signal. MAPS Provides software readable registers that report the difference between the arrival time of the J0 byte and the time JTAG CSU (x4) Microprocessor I/F the device frame reference expects to read the J0 byte from the ingress port FIFO on a per ingress port basis. PMC-2030715 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., Copyright PMC-Sierra, Inc. 2004 Issue 2 AND FOR ITS CUSTOMERS INTERNAL USE All rights reserved. TDO TDI TMS TCK TRSTB REFCLK P/ N 1..4 16-bit Microprocessor Bus RSTB INTB PM5377 TSE 240 Single Chip 96-Port STS-1/STM-0 Cross-Connect Provides 13 software configurable GENERAL APPLICATIONS delay registers for delay management RASIO 3G high-speed serial ingress SDH/SONET ADM blocks 1 through 13 to allow arbitrary and egress links. MSPP alignment of egress frames to the Low-power 1.2 V CMOS core logic Terminal Multiplexers device frame timing when DMO is with 2.5V digital outputs and 3.3V Digital Cross-Connects allocated to an egress port or group of tolerant 2.5V digital inputs. ports. 1152-pin FCBGA, 35 x 35 mm. PROTECTION SWITCHING Driven by a 155.52 MHz reference Implements Message Assisted clock. Protection Switching (MAPS) enabling Provides a standard five signal IEEE hardware based protection decisions 1149.1 JTAG test port for boundary and switching. scan board test. Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring. 23 W typical power consumption when all features and links 2.488 Gbit/s are enabled and active. TYPICAL APPLICATION 2x OC192/STM64 24x 10/100 Ethernet PM5326 PM5329 ARROW 2x192 ARROW 24xFE or w 8x OC48/STM16 p PM5377 TSE 240 2x OC192/STM64 8x 10/100 Ethernet PM5326 PM5333 ARROW 2x192 ARROW 8xFE or 8x OC48/STM16 ESSI links 2.5G or 622M 1x OC192/STM64 PM5324 Generic ESSI ARROW 1x192 Function or 4x OC48/STM16 PM5369 PM5369 PM5317 PM5369 TUPP 9953 1x OC192/STM64 PM5307 PM5369 TUPP 9953 SPECTRA TUPP 9953 TBS 9953 TUPP 9953 or 9953 4x OC48/STM16 PM5315 1x OC48/STM16 PM5309 SPECTRA TBS 2488 PM5370 or 2488 4x OC12/STM4 WSE 40 VT switching subsystem Head Office: To order documentation, All product documentation is available PMC-2030715(R2) PMC-Sierra, Inc. send email to: on our web site at: Copyright PMC-Sierra, Inc. 2004. All 8555 Baxter Place document pmc-sierra.com