UTOPIA Level 3/POS-PHY Level 3 System Interface Path Crossbar/ APS Cross-connect Serial Line Interface PM5380 Released S/UNI 8x155 8-Channel OC-3c ATM and POS Physical Layer Device Provides UTOPIA Level 3 32-bit wide Low power 2.5/3.3 V CMOS core logic FEATURES System Interface (clocked up to with 5V TTL compatible digital inputs Single chip 8-channel ATM and POS and digital outputs. PECL inputs and 104 MHz) with parity support for ATM User Network Interface operating at applications. outputs are 3.3 V and 5 V compatible. 155 Mbit/s with on-chip clock and data Provides SATURN POS-PHY Industrial temperature range (-40 C to recovery and clock synthesis for direct Level 3 32-bit System Interface +85 C). connection to optical modules. (clocked up to 104 MHz) for Packet 520-pin SBGA package. Implements the ATM Forum User over SONET (POS), or ATM Software compatible with the PM5358 Network Interface Specification and applications. S/UNI 4x622. the ATM physical layer for Broadband Supports line loopback from the line Pin compatible with PM5382 ISDN according to ITU side receive stream to the transmit S/UNI 16x155. Recommendation I.432. stream and diagnostic loopback from Implements the Point-to-Point Protocol DEVICE INTERNETWORKING the line side transmit stream to the line (PPP) over SONET/SDH specification side receive stream interface. Other PMC-Sierra devices that according to RFC 2615(1619)/1662 of implement the POS-PHY Level 3 Provides support for automatic the PPP Working Group of the Internet interface include: protection switching including a bi- Engineering Task Force (IETF). S/UNI 12xJET directional 2-bit PECL 622 MHz port Processes eight bit-serial 155 Mbit/s S/UNI 4x622 for external APS with mate device. STS-3c (STM-1) data streams with on- S/UNI 2488 Built-in APS cross-connect for internal chip clock and data recovery and clock S/UNI 2xGE and external 1+1 and 1:n protection synthesis. switching. S/UNI MACH48 Complies with Bellcore GR-253-CORE Provides a standard five signal IEEE S/UNI ATLAS 3200 (2000 issue) jitter tolerance, jitter 1149.1 JTAG test port for boundary S/UNI 16x155 transfer (1995 issue), and intrinsic jitter scan board test purposes. criteria. Provides a generic 8-bit Each channel provides termination for APPLICATIONS microprocessor bus interface for SONET Section, Line, and Path configuration, control, and status WAN and Edge ATM switches. overhead or SDH Regenerator monitoring. LAN switches and hubs. Section, Multiplexer Section, and High Packet switches and hubs. Order Path overhead. Routers and Layer 3 Switches. Network interface cards and uplinks. BLOCK DIAGRAM TFC LK TEN B Section/ L in e DCC TAD R 2:0 Insertion TSX Tx P O S TC A/TPA TXD 7:0 +/- Fram e Processor STPA RXD 7:0 +/- T x S ectio n TSO C /TSO P Tx L in e O /H Tx P a th O /H S D 7 :0 O/H TPR TY Processor Processor REFCLK+/- Processor Tx A T M TD AT 31:0 Cell T M O D 1 :0 Processor TEO P Section WAN ATB 1:0 P a th T race TER R T race Synch. B u ffe r B u ffe r RFCLK Rx A T M Cell RENB Q AVD Processor Q AVS RADR 2:0 R x S ectio n A V D 8 :0 RSX Rx L in e O /H Rx P a th O /H O/H AVS 8:0 Processor Processor RCA/RVAL Processor Rx P O S RSO C/RSO P Fram e RPRTY Processor SPEC LV R D AT 31:0 Section/ Sync R M O D 1 :0 SD TTL L in e DCC Status, REO P Extraction BERM RERR JT AG Ex te rn a l APS M icroprocessor T est A ccess Interface Interface Port PMC-2021288 (R1) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS INTERNAL USE Copyright PMC-Sierra, Inc. 2002 RALRM 7:0 TFPI RFPO TFPO RCLK TCLK RDCLK 7:0 TDCC 7:0 RDCC 7:0 TDCLK 7:0 TDO TRSTB TMS TDI TCK APREF0, APREF1 APECLV APSI 1:0 +/- APSO 1:0 +/- D 7:0 A 13:0 ALE CSB WRB RDB RSTB INTB POS ATMBReleased PM5380 S/UNI 8x155 8-Channel OC-3c ATM and POS Physical Layer Device TYPICAL APPLICATIONS STS-3C/STM-1 PACKET-OVER-SONET/SDH STS-3C/STM-1 ATM SWITCH PORT POS-PHY Level 3 Interface Link Layer PM5380 Utopia Level 3 Interface Device S/UNI-8x155 PM5380 ATM Layer TFCLK TFCLK S/UNI-8x155 Device TENB TENB TFCLK TFCLK TSX TSX TENB TENB TPRTY TPRTY TADR 2:0 TADR 2:0 TDAT 31:0 TDAT 31:0 TCA TCA RXD 0 +/- RXD 0 +/- Optical Optical TMOD 1:0 TMOD 1:0 TSOC TSOC SD 0 Transceiver SD 0 Transceiver 1 TSOP TSOP 1 TPRTY TPRTY TXD 0 +/- TXD 0 +/- TEOP TEOP TDAT 31:0 TDAT 31:0 RFCLK TERR TERR RFCLK TADR 2:0 RENB RENB TADR 2:0 RADR 2:0 RADR 2:0 PTPA PTPA RXD 7 +/- RXD 7 +/- RCA STPA STPA RCA Optical Optical SD 7 Transceiver SD 7 Transceiver RFCLK RFCLK RSOC RSOC 8 8 TXD 7 +/- TXD 7 +/- RENB RENB RPRTY RPRTY RADR 2:0 RADR 2:0 RDAT 31:0 RDAT 31:0 RSX RSX RVAL RVAL RPRTY RPRTY RDAT 31:0 RDAT 31:0 RSOP RSOP REOP REOP RERR RERR S/UNI-8X155 JITTER TOLERANCE PLOT Framed Jitter Tolerance (Synchronous, With OA) under Nominal Condition 100 10 1 0.1 10 100 1000 10000 100000 1000000 10000000 Frequency (Hz) Head Office: To order documentation, All product documentation is available PMC-2021288 (R1) PMC-Sierra, Inc. send email to: on our web site at: Copyright PMC-Sierra, 8555 Baxter Place document pmc-sierra.com