PM7366 PMC-Sierra,Inc. FREEDM-8 Frame Engine and Datalink Manager Supports a mix of channelized and Supports scatter-gather capabilities FEATURES unchannelized links. whereby a packet can span multiple High density HDLC controller ideal for buffers. The maximum aggregate clock rate is Internet access, Frame Relay, and 64 MHz. When the device is interfaced Supports line-side loopback on a per- DSLAM equipment supporting rates to two T3 or HSSI links, the maximum link basis and system-side loopback on ranging from 56 Kbit/s to 52 Mbit/s. aggregate clock rate is 104 MHz. a per-HDLC channel basis. Supports eight full-duplex and For channelized operation, the channel Pin-compatible and software- independently-timed links. assignment supports up to 24 timeslots compatible with the PM7364 Supports 128 full-duplex HDLC or for a T1 link and 31 timeslots for an E1 FREEDM-32. transparent channels. link. Timeslots assigned to a common Provides a standard 5-signal P1149.1 Supports a TimePipe architecture HDLC channel can be noncontiguous. JTAG test port for boundary scan test that enables any physical link to be Performs flag delineation, bit de- board purposes. flexibly mapped to one or more HDLC stuffing, CRC verification using either Implemented in low power 3.3 V channels. CRC-32 or CRC-CCITT algorithm, and CMOS technology with 5 V-tolerant Provides 8 KB partial packet FIFO in length checking on receive HDLC inputs. each transmit and receive direction to channels. Packaged in a 256-pin Ball Grid Array compensate for PCI bus latency during Performs flag insertion, bit stuffing, and (BGA) package. data transfers. The 8 KB partial packet FCS calculation using either CRC-32 FIFO is arranged as 512 blocks of 16- or CRC-CCITT algorithm and length APPLICATIONS byte buffers. checking on transmit HDLC channels. Ideal for applications requiring HDLC, The TimePipe architecture supports On the system side, provides a PPP, and transparent protocol programmable assignment of partial 33 MHz, 32-bit PCI 2.1-compliant bus processing for physical links, such as packet buffers to HDLC channels. interface. T1, E1, T3, E3, xDSL, and HSSI. Two physical links can support up to Implements efficient transmit and Frame-Based Interfaces for Internet 52 Mbit/s the remaining six physical receive DMA controllers to support Access and DSLAM equipment. links can individually support up to burst data transfers between partial FUNI or Frame Relay service 10 Mbit/s. packet FIFO and packet memory. interworking interfaces for ATM switches and multiplexers. BLOCK DIAGRAM AD 31:0 C/BEB 3:0 PAR FRAMEB RD 7:0 RHDL RMAC TRDYB RCAS Receive HDLC Receive Receive IRDYB Processor/ DMA Channel Assigner STOPB Partial Packet Buffer RCLK 7:0 Controller DEVSELB PMON IDSEL GPIC Performance Monitor PCI LOCKB Controller REQB TD 7:0 THDL TCAS TMAC GNTB Transmit HDLC Transmit Transmit PERRB Processor/ Channel Assigner DMA Partial Packet Buffer SERRB TCLK 7:0 Controller PCIINTB TimePipe Architecture PCICLK PCICLKO JTAG Port SYSCLK PMC-1970532 (R4) 2001 PMC-Sierra, Inc. RBD TBD RBCLK TBCLK TRSTB TMB TCK TDI TDO PMCTEST PM7366 FREEDM-8 Frame Engine and Datalink Manager TYPICAL APPLICATIONS HIGH DENSITY CHANNELIZED AND UNCHANNELIZED T1/E1 INTERFACES PCI Bus PM4354 4 x T1/E1 COMET- Processor QUAD PM7366 FREEDM-8 PM4354 4 x T1/E1 Packet COMET- Memory QUAD DS3/E3/J2 UPLINK INTERFACES PCI Bus DS3/E3/J2 LIU Processor PM7346 PM7366 S/UNI-QJET FREEDM-8 Packet DS3/E3/J2 Memory LIU Head Office: To order documentation, All product documentation is available PMC-1970532 (R4) PMC-Sierra, Inc. send email to: on our web site at: 2001 PMC-Sierra, Inc. 8555 Baxter Place document pmc-sierra.com