512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories Data Sheet FEATURES: Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 Fast Erase and Byte-Program: Single Voltage Read and Write Operations Sector-Erase Time: 18 ms (typical) Chip-Erase Time: 70 ms (typical) 3.0-3.6V for SST39LF512/010/020/040 Byte-Program Time: 14 s (typical) 2.7-3.6V for SST39VF512/010/020/040 Chip Rewrite Time: Superior Reliability 1 second (typical) for SST39LF/VF512 Endurance: 100,000 Cycles (typical) 2 seconds (typical) for SST39LF/VF010 Greater than 100 years Data Retention 4 seconds (typical) for SST39LF/VF020 Low Power Consumption 8 seconds (typical) for SST39LF/VF040 (typical values at 14 MHz) Automatic Write Timing Active Current: 5 mA (typical) Internal V Generation PP Standby Current: 1 A (typical) End-of-Write Detection Sector-Erase Capability Toggle Bit Uniform 4 KByte sectors Data Polling Fast Read Access Time: CMOS I/O Compatibility 45 ns for SST39LF512/010/020/040 JEDEC Standard 55 ns for SST39LF020/040 Flash EEPROM Pinouts and command sets 70 ns for SST39VF512/010/020/040 Packages Available Latched Address and Data 32-lead PLCC 32-lead TSOP (8mm x 14mm) 48-ball TFBGA (6mm x 8mm) 34-ball WFBGA (4mm x 6mm) for 1M and 2M All devices are RoHS compliant PRODUCT DESCRIPTION The SST39LF512, SST39LF010, SST39LF020, SST39LF040 ration, or data memory. For all system applications, they and SST39VF512, SST39VF010, SST39VF020, SST39VF040 significantly improves performance and reliability, while low- are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Pur- ering power consumption. They inherently use less energy pose Flash (MPF) manufactured with SSTs proprietary, high per- during Erase and Program than alternative flash technolo- formance CMOS SuperFlash technology. The split-gate cell gies. The total energy consumed is a function of the design and thick-oxide tunneling injector attain better reliability and applied voltage, current, and time of application. Since for manufacturability compared with alternate approaches. The any given voltage range, the SuperFlash technology uses SST39LF512/010/020/040 devices write (Program or Erase) with less current to program and has a shorter erase time, the a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices total energy consumed during any Erase or Program oper- write with a 2.7-3.6V power supply. The devices conform to ation is less than alternative flash technologies. These JEDEC standard pinouts for x8 memories. devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. Featuring high performance Byte-Program, the SST39LF512/010/020/040 and SST39VF512/010/020/ The SuperFlash technology provides fixed Erase and Pro- 040 devices provide a maximum Byte-Program time of 20 gram times, independent of the number of Erase/Program sec. These devices use Toggle Bit or Data Polling to indi- cycles that have occurred. Therefore the system software cate the completion of Program operation. To protect or hardware does not have to be modified or de-rated as is against inadvertent write, they have on-chip hardware and necessary with alternative flash technologies, whose Erase Software Data Protection schemes. Designed, manufac- and Program times increase with accumulated Erase/Pro- tured, and tested for a wide spectrum of applications, they gram cycles. are offered with a guaranteed typical endurance of To meet surface mount requirements, the SST39LF512/ 100,000 cycles. Data retention is rated at greater than 100 010/020/040 and SST39VF512/010/020/040 devices are years. offered in 32-lead PLCC and 32-lead TSOP packages. The The SST39LF512/010/020/040 and SST39VF512/010/ SST39LF/VF010 and SST39LF/VF020 are also offered in 020/040 devices are suited for applications that require a 48-ball TFBGA package. See Figures 2, 3, 4, and 5 for convenient and economical updating of program, configu- pin assignments. 2010 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71150-14-000 01/10 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet edge of the sixth WE pulse. The internal Erase operation Device Operation begins after the sixth WE pulse. The End-of-Erase can be Commands are used to initiate the memory operation func- determined using either Data Polling or Toggle Bit meth- tions of the device. Commands are written to the device ods. See Figure 11 for timing waveforms. Any commands using standard microprocessor write sequences. A com- written during the Sector-Erase operation will be ignored. mand is written by asserting WE low while keeping CE low. The address bus is latched on the falling edge of WE Chip-Erase Operation or CE , whichever occurs last. The data bus is latched on the rising edge of WE or CE , whichever occurs first. The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the 1s Read state. This is useful when the entire device must be quickly The Read operation of the SST39LF512/010/020/040 and erased. SST39VF512/010/020/040 device is controlled by CE and OE , both have to be low for the system to obtain data The Chip-Erase operation is initiated by executing a six- from the outputs. CE is used for device selection. When byte Software Data Protection command sequence with CE is high, the chip is deselected and only standby power Chip-Erase command (10H) with address 5555H in the last is consumed. OE is the output control and is used to gate byte sequence. The internal Erase operation begins with data from the output pins. The data bus is in high imped- the rising edge of the sixth WE or CE , whichever occurs ance state when either CE or OE is high. Refer to the first. During the internal Erase operation, the only valid read Read cycle timing diagram for further details (Figure 6). is Toggle Bit or Data Polling. See Table 4 for the command sequence, Figure 12 for timing diagram, and Figure 20 for the flowchart. Any commands written during the Chip- Byte-Program Operation Erase operation will be ignored. The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are programmed on a byte-by-byte basis. Before Write Operation Status Detection programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in The SST39LF512/010/020/040 and SST39VF512/010/ three steps. The first step is the three-byte load sequence 020/040 devices provide two software means to detect the for Software Data Protection. The second step is to load completion of a Write (Program or Erase) cycle, in order to byte address and byte data. During the Byte-Program optimize the system write cycle time. The software detec- operation, the addresses are latched on the falling edge of tion includes two status bits: Data Polling (DQ ) and Tog- 7 either CE or WE , whichever occurs last. The data is gle Bit (DQ ). The End-of-Write detection mode is enabled 6 latched on the rising edge of either CE or WE , whichever after the rising edge of WE which initiates the internal Pro- occurs first. The third step is the internal Program operation gram or Erase operation. which is initiated after the rising edge of the fourth WE or The actual completion of the nonvolatile write is asynchro- CE , whichever occurs first. The Program operation, once nous with the system therefore, either a Data Polling or initiated, will be completed, within 20 s. See Figures 7 and Toggle Bit read may be simultaneous with the completion 8 for WE and CE controlled Program operation timing of the Write cycle. If this occurs, the system may possibly diagrams and Figure 17 for flowcharts. During the Program get an erroneous result, i.e., valid data may appear to con- operation, the only valid reads are Data Polling and Tog- flict with either DQ or DQ . In order to prevent spurious 7 6 gle Bit. During the internal Program operation, the host is rejection, if an erroneous result occurs, the software routine free to perform additional tasks. Any commands written should include a loop to read the accessed location an during the internal Program operation will be ignored. additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- Sector-Erase Operation tion is valid. The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector- Erase operation is initiated by executing a six-byte com- mand sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE pulse, while the command (30H) is latched on the rising 2010 Silicon Storage Technology, Inc. S71150-14-000 01/10 2