16 Mbit / 32 Mbit / (x16) Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202 SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories Data Sheet FEATURES: Organized as 1M x16: SST39VF1601/1602 Security-ID Feature 2M x16: SST39VF3201/3202 SST: 128 bits User: 128 bits Single Voltage Read and Write Operations Fast Read Access Time: 2.7-3.6V 70 ns Superior Reliability Latched Address and Data Endurance: 100,000 Cycles (Typical) Fast Erase and Word-Program: Greater than 100 years Data Retention Sector-Erase Time: 18 ms (typical) Low Power Consumption (typical values at 5 MHz) Block-Erase Time: 18 ms (typical) Active Current: 9 mA (typical) Chip-Erase Time: 40 ms (typical) Standby Current: 3 A (typical) Word-Program Time: 7 s (typical) Auto Low Power Mode: 3 A (typical) Automatic Write Timing Hardware Block-Protection/WP Input Pin Internal V Generation PP Top Block-Protection (top 32 KWord) End-of-Write Detection for SST39VF1602/3202 Toggle Bits Bottom Block-Protection (bottom 32 KWord) Data Polling for SST39VF1601/3201 CMOS I/O Compatibility Sector-Erase Capability JEDEC Standard Uniform 2 KWord sectors Flash EEPROM Pinouts and command sets Block-Erase Capability Packages Available Uniform 32 KWord blocks 48-lead TSOP (12mm x 20mm) Chip-Erase Capability 48-ball TFBGA (6mm x 8mm) Erase-Suspend/Erase-Resume Capabilities All non-Pb (lead-free) devices are RoHS compliant Hardware Reset Pin (RST ) PRODUCT DESCRIPTION The SST39VF160x and SST39VF320x devices are 1M The SST39VF160x/320x devices are suited for applica- x16 and 2M x16, respectively, CMOS Multi-Purpose tions that require convenient and economical updating of Flash Plus (MPF+) manufactured with SSTs proprietary, program, configuration, or data memory. For all system high performance CMOS SuperFlash technology. The applications, they significantly improve performance and split-gate cell design and thick-oxide tunneling injector reliability, while lowering power consumption. They inher- attain better reliability and manufacturability compared ently use less energy during Erase and Program than alter- with alternate approaches. The SST39VF160x/320x write native flash technologies. The total energy consumed is a (Program or Erase) with a 2.7-3.6V power supply. These function of the applied voltage, current, and time of applica- devices conform to JEDEC standard pinouts for x16 tion. Since for any given voltage range, the SuperFlash memories. technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Featuring high performance Word-Program, the Program operation is less than alternative flash technolo- SST39VF160x/320x devices provide a typical Word-Pro- gies. These devices also improve flexibility while lowering gram time of 7 sec. These devices use Toggle Bit or the cost for program, data, and configuration storage appli- Data Polling to indicate the completion of Program opera- cations. tion. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. The SuperFlash technology provides fixed Erase and Pro- Designed, manufactured, and tested for a wide spectrum of gram times, independent of the number of Erase/Program applications, these devices are offered with a guaranteed cycles that have occurred. Therefore the system software typical endurance of 100,000 cycles. Data retention is rated or hardware does not have to be modified or de-rated as is at greater than 100 years. necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. 2008 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71223-05-000 6/08 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.16 Mbit / 32 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202 Data Sheet To meet high density, surface mount requirements, the s. See Figures 5 and 6 for WE and CE controlled Pro- SST39VF160x/320x are offered in 48-lead TSOP and gram operation timing diagrams and Figure 20 for flow- 48-ball TFBGA packages. See Figures 2 and 3 for pin charts. During the Program operation, the only valid reads assignments. are Data Polling and Toggle Bit. During the internal Pro- gram operation, the host is free to perform additional tasks. Any commands issued during the internal Program opera- Device Operation tion are ignored. During the command sequence, WP Commands are used to initiate the memory operation func- should be statically held high or low. tions of the device. Commands are written to the device using standard microprocessor write sequences. A com- Sector/Block-Erase Operation mand is written by asserting WE low while keeping CE low. The address bus is latched on the falling edge of WE The Sector- (or Block-) Erase operation allows the system or CE , whichever occurs last. The data bus is latched on to erase the device on a sector-by-sector (or block-by- the rising edge of WE or CE , whichever occurs first. block) basis. The SST39VF160x/320x offer both Sector- Erase and Block-Erase mode. The sector architecture is The SST39VF160x/320x also have the Auto Low Power based on uniform sector size of 2 KWord. The Block-Erase mode which puts the device in a near standby mode after mode is based on uniform block size of 32 KWord. The data has been accessed with a valid Read operation. This Sector-Erase operation is initiated by executing a six-byte reduces the I active read current from typically 9 mA to DD command sequence with Sector-Erase command (30H) typically 3 A. The Auto Low Power mode reduces the typi- and sector address (SA) in the last bus cycle. The Block- cal I active read current to the range of 2 mA/MHz of DD Erase operation is initiated by executing a six-byte com- Read cycle time. The device exits the Auto Low Power mand sequence with Block-Erase command (50H) and mode with any address transition or control signal transition block address (BA) in the last bus cycle. The sector or block used to initiate another Read cycle, with no access time address is latched on the falling edge of the sixth WE penalty. Note that the device does not enter Auto-Low pulse, while the command (30H or 50H) is latched on the Power mode after power-up with CE held steadily low, rising edge of the sixth WE pulse. The internal Erase until the first address transition or CE is driven high. operation begins after the sixth WE pulse. The End-of- Erase operation can be determined using either Data Read Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms and Figure 24 for the flowchart. Any The Read operation of the SST39VF160x/320x is con- commands issued during the Sector- or Block-Erase oper- trolled by CE and OE , both have to be low for the sys- ation are ignored. When WP is low, any attempt to Sector- tem to obtain data from the outputs. CE is used for (Block-) Erase the protected block will be ignored. During device selection. When CE is high, the chip is dese- the command sequence, WP should be statically held lected and only standby power is consumed. OE is the high or low. output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the Read cycle timing Erase-Suspend/Erase-Resume Commands diagram for further details (Figure 4). The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be Word-Program Operation read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The SST39VF160x/320x are programmed on a word-by- The operation is executed by issuing one byte command word basis. Before programming, the sector where the sequence with Erase-Suspend command (B0H). The word exists must be fully erased. The Program operation is device automatically enters read mode typically within 20 accomplished in three steps. The first step is the three-byte s after the Erase-Suspend command had been issued. load sequence for Software Data Protection. The second Valid data can be read from any sector or block that is not step is to load word address and word data. During the suspended from an Erase operation. Reading at address Word-Program operation, the addresses are latched on the location within erase-suspended sectors/blocks will output falling edge of either CE or WE , whichever occurs last. DQ toggling and DQ at 1. While in Erase-Suspend The data is latched on the rising edge of either CE or 2 6 mode, a Word-Program operation is allowed except for the WE , whichever occurs first. The third step is the internal sector or block selected for Erase-Suspend. Program operation which is initiated after the rising edge of the fourth WE or CE , whichever occurs first. The Pro- gram operation, once initiated, will be completed within 10 2008 Silicon Storage Technology, Inc. S71223-05-000 6/08 2