16 Mbit (x16) Multi-Purpose Flash Plus SST39VF1601C / SST39VF1602C SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories Data Sheet FEATURES: Organized as 1M x16: SST39VF1601C/1602C Security-ID Feature Single Voltage Read and Write Operations SST: 128 bits User: 128 words 2.7-3.6V Fast Read Access Time: Superior Reliability 70 ns Endurance: 100,000 Cycles (Typical) Fast Erase and Word-Program: Greater than 100 years Data Retention Sector-Erase Time: 18 ms (typical) Low Power Consumption (typical values at 5 MHz) Block-Erase Time: 18 ms (typical) Chip-Erase Time: 40 ms (typical) Active Current: 9 mA (typical) Word-Program Time: 7 s (typical) Standby Current: 3 A (typical) Auto Low Power Mode: 3 A (typical) Automatic Write Timing Hardware Block-Protection/WP Input Pin Internal V Generation PP Top Block-Protection (top 8 KWord) End-of-Write Detection Bottom Block-Protection (bottom 8 KWord) Toggle Bits Sector-Erase Capability Data Polling Ready/Busy Pin Uniform 2 KWord sectors CMOS I/O Compatibility Block-Erase Capability JEDEC Standard Flexible block architecture one 8-, two 4-, one 16-, and thirty one 32-KWord blocks Flash EEPROM Pinouts and command sets Chip-Erase Capability Packages Available Erase-Suspend/Erase-Resume Capabilities 48-lead TSOP (12mm x 20mm) 48-ball TFBGA (6mm x 8mm) Hardware Reset Pin (RST ) 48-ball WFBGA (4mm x 6mm) Latched Address and Data All devices are RoHS compliant PRODUCT DESCRIPTION The SST39VF1601C and SST39VF1602C devices are reliability, while lowering power consumption. They inher- 1M x16 CMOS Multi-Purpose Flash Plus (MPF+) manu- ently use less energy during Erase and Program than alter- factured with SST proprietary, high performance CMOS native flash technologies. The total energy consumed is a SuperFlash technology. The split-gate cell design and function of the applied voltage, current, and time of applica- thick-oxide tunneling injector attain better reliability and tion. Since for any given voltage range, the SuperFlash manufacturability compared with alternate approaches. technology uses less current to program and has a shorter The SST39VF160xC writes (Program or Erase) with a erase time, the total energy consumed during any Erase or 2.7-3.6V power supply. These devices conform to JEDEC Program operation is less than alternative flash technolo- standard pinouts for x16 memories. gies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage appli- Featuring high performance Word-Program, the cations. SST39VF1601C/1602C devices provide a typical Word- Program time of 7 sec. These devices use Toggle Bit, The SuperFlash technology provides fixed Erase and Pro- Data Polling, or the RY/BY pin to indicate the completion gram times, independent of the number of Erase/Program of Program operation. To protect against inadvertent write, cycles that have occurred. Therefore the system software they have on-chip hardware and Software Data Protection or hardware does not have to be modified or de-rated as is schemes. Designed, manufactured, and tested for a wide necessary with alternative flash technologies, whose spectrum of applications, these devices are offered with a Erase and Program times increase with accumulated guaranteed typical endurance of 100,000 cycles. Data Erase/Program cycles. retention is rated at greater than 100 years. To meet high density, surface mount requirements, the The SST39VF1601C/1602C devices are suited for applica- SST39VF1601C/1602C are offered in 48-lead TSOP, 48- tions that require convenient and economical updating of ball TFBGA, and 48-ball WFBGA packages. See Figures program, configuration, or data memory. For all system 2, 3, and 4 for pin assignments. applications, they significantly improve performance and 2010 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71380-04-000 05/10 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.16 Mbit Multi-Purpose Flash Plus SST39VF1601C / SST39VF1602C Data Sheet Device Operation Commands are used to initiate the memory operation func- Any commands issued during the internal Program opera- tions of the device. Commands are written to the device tion are ignored. During the command sequence, WP using standard microprocessor write sequences. A com- should be statically held high or low. mand is written by asserting WE low while keeping CE low. The address bus is latched on the falling edge of WE Sector/Block-Erase Operation or CE , whichever occurs last. The data bus is latched on The Sector- (or Block-) Erase operation allows the system the rising edge of WE or CE , whichever occurs first. to erase the device on a sector-by-sector (or block-by- The SST39VF1601C/1602C also have the Auto Low block) basis. The SST39VF1601C/1602C offer both Sec- Power mode which puts the device in a near standby mode tor-Erase and Block-Erase mode. after data has been accessed with a valid Read operation. The sector architecture is based on a uniform sector size of This reduces the I active read current from typically 9 mA DD 2 KWord. The Block-Erase mode is based on non-uniform to typically 3 A. The Auto Low Power mode reduces the block sizesthirty-one 32 KWord, one 16 KWord, two 4 typical I active read current to the range of 2 mA/MHz of DD KWord, and one 8 KWord blocks. See Figure 5 for top and Read cycle time. The device exits the Auto Low Power bottom boot device block addresses. The Sector-Erase mode with any address transition or control signal transition operation is initiated by executing a six-byte command used to initiate another Read cycle, with no access time sequence with Sector-Erase command (50H) and sector penalty. Note that the device does not enter Auto-Low address (SA) in the last bus cycle. The Block-Erase opera- Power mode after power-up with CE held steadily low, tion is initiated by executing a six-byte command sequence until the first address transition or CE is driven high. with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched Read on the falling edge of the sixth WE pulse, while the com- The Read operation of the SST39VF1601C/1602C is mand (30H or 50H) is latched on the rising edge of the controlled by CE and OE , both have to be low for the sixth WE pulse. The internal Erase operation begins after system to obtain data from the outputs. CE is used for the sixth WE pulse. The End-of-Erase operation can be device selection. When CE is high, the chip is dese- determined using either Data Polling or Toggle Bit meth- lected and only standby power is consumed. OE is the ods. See Figures 12 and 13 for timing waveforms and Fig- output control and is used to gate data from the output ure 26 for the flowchart. Any commands issued during the pins. The data bus is in high impedance state when Sector- or Block-Erase operation are ignored. When WP either CE or OE is high. Refer to the Read cycle timing is low, any attempt to Sector- (Block-) Erase the protected diagram for further details (Figure 6). block will be ignored. During the command sequence, WP should be statically held high or low. Word-Program Operation Erase-Suspend/Erase-Resume Commands The SST39VF1601C/1602C are programmed on a word- by-word basis. Before programming, the sector where the The Erase-Suspend operation temporarily suspends a word exists must be fully erased. The Program operation is Sector- or Block-Erase operation thus allowing data to be accomplished in three steps. The first step is the three-byte read from any memory location, or program data into any load sequence for Software Data Protection. The second sector/block that is not suspended for an Erase operation. step is to load word address and word data. During the The operation is executed by issuing one byte command Word-Program operation, the addresses are latched on the sequence with Erase-Suspend command (B0H). The falling edge of either CE or WE , whichever occurs last. device automatically enters read mode typically within 20 The data is latched on the rising edge of either CE or s after the Erase-Suspend command had been issued. WE , whichever occurs first. The third step is the internal Valid data can be read from any sector or block that is not Program operation which is initiated after the rising edge of suspended from an Erase operation. Reading at address the fourth WE or CE , whichever occurs first. The Pro- location within erase-suspended sectors/blocks will output gram operation, once initiated, will be completed within 10 DQ toggling and DQ at 1. While in Erase-Suspend 2 6 s. See Figures 7 and 8 for WE and CE controlled Pro- mode, a Word-Program operation is allowed except for the gram operation timing diagrams and Figure 22 for flow- sector or block selected for Erase-Suspend. charts. During the Program operation, the only valid reads are Data Polling and Toggle Bit. During the internal Pro- gram operation, the host is free to perform additional tasks. 2010 Silicon Storage Technology, Inc. S71380-04-000 05/10 2