16 Mbit (x16) Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 SST39WF160x2.7V 16Mb (x16) MPF+ memories Data Sheet FEATURES: Organized as 1M x16 Security-ID Feature Single Voltage Read and Write Operations SST: 128 bits User: 128 bits 1.65-1.95V Fast Read Access Time: Superior Reliability 70 ns Endurance: 100,000 Cycles (Typical) Latched Address and Data Greater than 100 years Data Retention Fast Erase and Word-Program: Low Power Consumption (typical values at 5 MHz) Sector-Erase Time: 36 ms (typical) Active Current: 5 mA (typical) Block-Erase Time: 36 ms (typical) Standby Current: 5 A (typical) Chip-Erase Time: 140 ms (typical) Auto Low Power Mode: 5 A (typical) Word-Program Time: 28 s (typical) Hardware Block-Protection/WP Input Pin Automatic Write Timing Top Block-Protection (top 32 KWord) Internal V Generation PP for SST39WF1602 End-of-Write Detection Bottom Block-Protection (bottom 32 KWord) Toggle Bits for SST39WF1601 Data Polling Sector-Erase Capability CMOS I/O Compatibility Uniform 2 KWord sectors JEDEC Standard Block-Erase Capability Flash EEPROM Pin Assignments and Uniform 32 KWord blocks Command Sets Chip-Erase Capability Packages Available Erase-Suspend/Erase-Resume Capabilities 48-ball TFBGA (6mm x 8mm) Hardware Reset Pin (RST ) 48-ball WFBGA (5mm x 6mm) 48-ball WFBGA (4mm x 6mm) All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST39WF1601/1602 devices are 1M x16 CMOS program, configuration, or data memory. For all system Multi-Purpose Flash Plus (MPF+) manufactured with applications, they significantly improve performance and SSTs proprietary, high-performance CMOS SuperFlash reliability, while lowering power consumption. They inher- technology. The split-gate cell design and thick-oxide tun- ently use less energy during Erase and Program than neling injector attain better reliability and manufacturability alternative flash technologies. The total energy consumed compared with alternate approaches. The SST39WF1601/ is a function of the applied voltage, current, and time of 1602 write (Program or Erase) with a 1.65-1.95V power application. Since for any given voltage range, the Super- supply. These devices conform to JEDEC standard pin Flash technology uses less current to program and has a assignments for x16 memories. shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash Featuring high performance Word-Program, the technologies. These devices also improve flexibility while SST39WF1601/1602 devices provide a typical Word-Pro- lowering the cost for program, data, and configuration stor- gram time of 28 sec. These devices use Toggle Bit or age applications. Data Polling to indicate the completion of Program opera- tion. To protect against inadvertent write, they have on-chip The SuperFlash technology provides fixed Erase and Pro- hardware and Software Data Protection schemes. gram times, independent of the number of Erase/Program Designed, manufactured, and tested for a wide spectrum of cycles that have occurred. Therefore the system software applications, these devices are offered with a guaranteed or hardware does not have to be modified or de-rated as is typical endurance of 100,000 cycles. Data retention is rated necessary with alternative flash technologies, whose at greater than 100 years. Erase and Program times increase with accumulated Erase/Program cycles. The SST39WF1601/1602 devices are suited for applica- tions that require convenient and economical updating of 2009 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71297-05-000 11/09 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet To meet high density, surface mount requirements, the Word-Program Operation SST39WF1601/1602 are offered in both 48-ball TFBGA The SST39WF1601/1602 are programmed on a word-by- and 48-ball WFBGA packages. See Figures 2 and 3 for word basis. Before programming, the sector where the pin assignments. word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte Device Operation load sequence for Software Data Protection. The second step is to load word address and word data. During the Commands are used to initiate the memory operation func- Word-Program operation, the addresses are latched on the tions of the device. Commands are written to the device falling edge of either CE or WE , whichever occurs last. using standard microprocessor write sequences. A com- The data is latched on the rising edge of either CE or mand is written by asserting WE low while keeping CE WE , whichever occurs first. The third step is the internal low. The address bus is latched on the falling edge of WE Program operation which is initiated after the rising edge of or CE , whichever occurs last. The data bus is latched on the fourth WE or CE , whichever occurs first. The Pro- the rising edge of WE or CE , whichever occurs first. gram operation, once initiated, will be completed within 40 The SST39WF1601/1602 also have the Auto Low Power s. See Figures 5 and 6 for WE and CE controlled Pro- mode which puts the device in a near standby mode after gram operation timing diagrams and Figure 20 for flow- data has been accessed with a valid Read operation. This charts. During the Program operation, the only valid reads reduces the I active read current from typically 9 mA to DD are Data Polling and Toggle Bit. During the internal Pro- typically 5 A. The Auto Low Power mode reduces the typi- gram operation, the host is free to perform additional tasks. cal I active read current to the range of 2 mA/MHz of DD Any commands issued during the internal Program opera- Read cycle time. The device exits the Auto Low Power tion are ignored. During the command sequence, WP mode with any address transition or control signal transition should be statically held high or low. used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Sector/Block-Erase Operation Power mode after power-up with CE held steadily low, until the first address transition or CE is driven high. The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST39WF1601/1602 offer both Sector- Read Erase and Block-Erase modes. The sector architecture is The Read operation of the SST39WF1601/1602 is con- based on uniform sector size of 2 KWord. The Block-Erase trolled by CE and OE , both have to be low for the sys- mode is based on uniform block size of 32 KWord. The tem to obtain data from the outputs. CE is used for Sector-Erase operation is initiated by executing a six-byte device selection. When CE is high, the chip is dese- command sequence with Sector-Erase command (30H) lected and only standby power is consumed. OE is the and sector address (SA) in the last bus cycle. The Block- output control and is used to gate data from the output Erase operation is initiated by executing a six-byte com- pins. The data bus is in high impedance state when mand sequence with Block-Erase command (50H) and either CE or OE is high. Refer to the Read cycle timing block address (BA) in the last bus cycle. The sector or block diagram for further details (Figure 4). address is latched on the falling edge of the sixth WE pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE pulse. The internal Erase operation begins after the sixth WE pulse. The End-of- Erase operation can be determined using either Data Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or Block-Erase oper- ation are ignored. When WP is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP should be statically held high or low. 2009 Silicon Storage Technology, Inc. S71297-05-000 11/09 2