NOT RECOMMENDED FOR NEW DESIGNS SY100S351 Micrel, Inc. HEX D FLIP-FLOP SY100S351 FEATURES DESCRIPTION Max. toggle frequency of 700MHz The SY100S351 offers six D-type, edge-triggered, master/ slave flip-flops with differential outputs, and is designed for Clock to Q max. of 1200ps use in high-performance ECL systems. The flip-flops are IEE min. of 98mA controlled by the signal from the logical OR operation on a Industry standard 100K ECL levels pair of common clock signals (CPa, CPb). Data enters the Extended supply voltage option: master when both CPa and CPb are LOW and transfers to the VEE = 4.2V to 5.5V slave when either CPa or CPb (or both) go to a logic HIGH. The Master Reset (MR) input overrides all other inputs and Voltage and temperature compensation for improved takes the Q outputs to a logic LOW. The inputs on this device noise immunity have 75k pull-down resistors. Internal 75k input pull-down resistors 50% faster than Fairchild 300K Better than 20% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 28-pin PLCC package BLOCK DIAGRAM PIN NAMES Pin Function D0 D5 Data Inputs CPa, CPb Common Clock Inputs MR Asynchronous Master Reset Input Q0 Q5 Data Outputs Q0 Q5 Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Rev.: I Amendment: /0 M9999-060910 1 Issue Date: June 2010 hbwhelp micrel.com or (408) 955-1690SY100S351 Micrel, Inc. PACKAGE/ORDERING INFORMATION Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish SY100S351JC J28-1 Commercial SY100S351JC Sn-Pb (1) SY100S351JCTR J28-1 Commercial SY100S351JC Sn-Pb (2) SY100S351JZ J28-1 Commercial SY100S351JZ with Matte-Sn Pb-Free bar-line indicator (1, 2) SY100S351JZTR J28-1 Commercial SY100S351JZ with Matte-Sn Pb-Free bar-line indicator (1) Matte-Sn SY100S351JY with SY100S351JY J28-1 Industrial Pb-Free bar-line indicator SY100S351JY with (1,2) Matte-Sn SY100S351JYTR Industrial J28-1 Pb-Free bar-line indicator Notes: 28-Pin PLCC (J28-1) 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. TRUTH TABLES (1) (1) Asynchronous Operation Synchronous Operation Inputs Outputs Inputs Outputs Dn CPa CP b MR Qn (t+1) Dn CPa CP b MR Qn (t+1) X X X H L L u L L L H u L L H NOTE: L L u L L 1. H = High Voltage Level H L u L H L = Low Voltage Level X = Don t Care X H u L Qn(t) t = Time before CP Positive Transition X u H L Qn(t) t+1 = Time after CP Positive Transition X L L L Qn(t) u = LOW-to-HIGH Transition M9999-060910 2 hbwhelp micrel.com or (408) 955-1690