SuperLite 3.3V, 2.5Gbps Micrel, Inc. SY55857L SuperLite ANY INPUT-to-LVPECL SY55857L DUAL TRANSLATOR FEATURES Input accepts virtually all logic standards: SuperLite Single-ended: SSTL, TTL, CMOS Differential: LVDS, HSTL, CML DESCRIPTION Guaranteed AC parameters over temperature: f > 2.5Gbps (2.5GHz toggle) MAX The SY55857L is a fully differential, high-speed dual t /t < 200ps r f translator optimized to accept any logic standard from Within-device skew < 50ps single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is Propagation delay < 400ps guaranteed for speeds up to 2.5Gbps (2.5GHz toggle Low power: 46mW/channel (typ) frequency). The SY55857L does not internally terminate 3.0V to 3.6V power supply its inputs, as different interfacing standards have different 100K LVPECL outputs termination requirements. All support documentation can be found on Micrels web Flow-through pinout and fully differential design site at www.micrel.com. Two channels in a 10-pin (3mm 3mm) MSOP package FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High-speed logic D0 Q0 Data communications systems Any IN CH0 LVPECL OUT Wireless communications systems /D0 /Q0 Telecom systems D1 Q1 Any IN CH1 LVPECL OUT /D1 /Q1 SuperLite is a trademark of Micrel, Inc. Rev.: E Amendment: /0 M9999-082306 1 Issue Date: August 2006 hbwhelp micrel.com or (408) 955-1690SuperLite Micrel, Inc. SY55857L PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead D0 1 10 VCC Part Number Type Range Marking Finish /D0 2 9 Q0 SY55857LKI K10-1 Industrial 857L Sn-Pb D1 3 8 /Q0 (2) SY55857LKITR K10-1 Industrial 857L Sn-Pb /D1 4 7 Q1 (3) SY55857LKG K10-1 Industrial 857L with NiPdAu GND 5 6 /Q1 Pb-Free bar line indicator Pb-Free (2, 3) SY55857LKGTR K10-1 Industrial 857L with NiPdAu 10-Pin MSOP (K10-1) Pb-Free bar line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. PIN DESCRIPTIONS Pin Number Pin Name Description D0, /D0 1, 2 Channel 0 Differential Inputs (clock or data). See Figure 2 for input structure. See Input Interface section for typical interface recommendations. D1, /D1 3, 4 Channel 1 Differential Inputs (clock or data). See Figure 2 for input structure. See Input Interface section for typical interface recommendations. Q0, /Q0 9, 8 Channel 0 Differential 100k-compatible LVPECL Outputs. Terminate to V 2V. See LVPECL Output Termination section. Outputs are low CC impedance, emitter-followers. For AC-coupled applications, a pull-down resistor is required on Q and /Q to ensure a DC current path to GND. Q1, /Q1 7, 6 Channel 1 Differential 100k-compatible LVPECL Outputs. Terminate to V 2V. See LVPECL Output Termination section. Outputs are low CC impedance, emitter-followers. For AC-coupled applications, a pull-down resistor is required on Q and /Q to ensure a DC current path to GND. GND 5 Device Ground. Typically connected to Logic ground. V 10 Supply Voltage. Typically connect to +3.3V 10% supply. Bypass with CC 0.01 F0.1 F low ESR capacitors. M9999-082306 2 hbwhelp micrel.com or (408) 955-1690