125MHz TRIGGER SY604 PROGRAMMABLE TIMING FINAL EDGE VERNIER FEATURES DESCRIPTION True 125MHz retrigger rate Micrel-Synergy s SY604 is an ECL-compatible timing vernier (delay generator) whose time delay is programmed via an 8- Pin-compatible with Bt604 bit code which is loaded concurrently with the circuit trigger. 15ps delay resolution The SY604 is fabricated in Micrel-Synergy s proprietary ASSET bipolar process. Less than 1 LSB timing accuracy This device can be retriggered at speeds up to 125MHz, Differential TRIGGER inputs with a delay span as short as 4ns. At minimum span, the Delay spans from 4 to 40ns resolution is 4ns/255 = 15.7ps per step. The delay span is externally adjustable up to 40ns. The SY604 employs Compatible with 10KH ECL logic differential TRIGGER inputs, and produces a differential Lower power dissipation 350mW typical OUTPUT pulse all other control signals are single-ended Available in 28-pin plastic (PLCC) or metal (MLCC) ECL. Edge delay is specified by an 8-bit input which is loaded J-lead package into the device with the TRIGGER. The output pulse width will typically be 3.5ns. The SY604 is commonly used in Automatic Test Equipment to provide precise timing edge placement it is also found in BLOCK DIAGRAM many instrumentation and communications applications. Micrel-Synergy s circuit design techniques coupled with ASSET technology result in not only ultra-fast performance, but allow device operation at lower power dissipation than competing technologies. Outstanding reliability is achieved in 8 8 I/V D0 - D7 DAC LATCH volume production. PIN CONFIGURATION + PULSE OUT GEN VBB LINEAR D RAMP CE GENERATOR 0 = STOP FF 25 24 23 22 21 20 19 1 = RUN D0 26 18 NC R TRIG 27 D1 17 COMP2 D2 28 16 CE TOP VIEW D3 1 15 COMP1 PLCC 2 D4 J28-1 14 NC D5 3 13 VBB IEXT D6 4 12 IEXT 56 8 10 11 7 9 Rev.: E Amendment: /0 Issue Date: May, 1998 1 VCC D7 VEE1 VCC VEE1 OUT TRIG OUT VCC TRIG VCC VEE0 NC VEE0SY604 Micrel PIN DESCRIPTION D0 D7 OUT, OUT Data input pins (ECL compatible). On the rising edge of TRIG, Differential outputs (ECL compatible). a ramp is initiated whereupon D0-D7 are latched into the device. D0 is the LSB. These inputs specify the amount of IEXT delay from the rising edge of TRIG to the output pulse. Current reference pin. The amount of current sourced into this pin determines the span of output delay. The voltage at IEXT CE is typically 1.25V. Chip enable input (ECL compatible). CE must be a logical zero on the rising edge of TRIG to enable the device to COMP1, COMP2 respond to the trigger. If CE is floating, the trigger will always Compensation pins. A 0.1 F ceramic capacitor must be be enabled. connected between COMP1 and VEE0, and COMP2 and VEE0 (see Figure 3). TRIG, TRIG Differential trigger inputs (ECL compatible). The rising edge VEE of TRIG is used to trigger the delay cycle if CE is a logical zero. Device power. All VEE pins must be connected. If CE is a logical one, no operation occurs. It is recommended that triggering be performed with differential inputs. VCC Device ground. All VCC pins must be connected together. VBB A 1.36V (typical) output. FUNCTIONAL DESCRIPTION The output pulse generation cycle begins with the arrival of When the ramp level reaches that of the DAC, the TRIG shown in Figure 1. When TRIG transitions to a high and comparator initiates the pulse generator to produce an output CE is low, the values on D0 - D7 are latched, thereby setting pulse of fixed width. The generation of an output pulse resets the DAC values. Simultaneously with the latching of D0 - D7, the ramp and the cycle is ready to begin again. the linear ramp generator is enabled. DATA D0 - D7 CE TRIG OUT Figure 1. 2