SY88063CLMG Microchip

SY88053CL 1.0625G to 12.5G Limiting Post Amplifier with Programmable Decision Threshold Revision 1.0 Features General Description Multi-rate operation from 1.0625Gbps to 12.5Gbps The SY88053CL limiting post amplifier is designed for use Adjustable decision threshold level for offset in fiber-optic receivers for multi-rate applications from compensation or BER optimization 1.0625Gbps to 12.5Gbps. Wide differential input range (5mV to 1800mV ) PP PP The SY88053CL contains a high-bandwidth, high- Wide SD de-assert or LOS assert threshold range sensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables 3mV to 30mV PP PP optimized system reach. Typically, 4dB of electrical 4dB typical electrical hysteresis hysteresis is provided to minimize LOS or SD chattering Fast SD assert and LOS de-assert times caused by noisy input signals. A logic level control pin is 75ns typical 120ns maximum provided to enable user selection of an open-collector, Selectable LOS or SD status signal indicator TTL-compatible LOS or SD status indication signal with an external 5k to 10k pull-up resistor. Selectable RXOUT+/RXOUT polarity inversion TTL-compatible JAM input with internal pull-up The SY88053CL provides fast SD assert and LOS de- assert times over the entire differential input voltage range Low-noise CML data inputs with integrated 50 of 5mV to 1800mV . termination impedance to internal reference V PP PP REF Low-noise CML data outputs with integrated 50 The SY88053CL input stage also provides a user- termination impedance adjustable decision threshold circuit to optimize BER in noisy applications such as WDM, where EDFA and Raman 25ps typical rise/fall times amplifiers contribute uneven noise levels. By applying an Wide range power supply: 3.3V 10% external control voltage, the decision threshold can Industrial temperature range: 40C to +85C typically be adjusted from 30% to 70% from the nominal Available in a tiny 3mm x 3mm QFN package 50% threshold when the circuit is disabled. Applications The SY88053CL provides integrated 50 input and output impedances to optimize the high-speed signal paths and Asymmetrical/Symmetrical 10GEPON reduce component count. The post amplifier outputs have Asymmetrical/Symmetrical XGPON user-selectable polarity inversion control to simplify PCB 10Gigabit Ethernet layout. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD 8Gbps and 10Gbps Fibre Channel signal. The JAM input disables only the post amplifier SONET OC192 SDH STM64 output. WDM/DWDM systems The SY88053CL operates from a single +3.3V power Markets supply, over temperatures ranging from 40C to +85C. PON/FTTx Datasheets and support documentation are available on Micrels web site at: www.micrel.com. Datacom/Enterprise Storage area networks High-performance computing Telecom 8G+ Optical transceivers . Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY88053CL Typical Application Circuit Fixed Decision Threshold Typical Application Circuit Adjustable Decision Threshold Revision 1.0 July 3, 2013 2 FOMhelp micrel.com or (408) 955-1690