SY89297UMG Microchip

SY89297U 2.5V/3.3V, 3.2 Gbps, Precision CML Dual-Channel Programmable Delay Features General Description Dual-Channel, Programmable Delay Line The SY89297U is a DC-3.2Gbps programmable, two-channel delay line. Each channel has a delay Serial Programming Interface (SDATA, SCLK, range from 2ns to 7ns (5ns delta delay) in SLOAD) programmable increments as small as 5 ps. The delay Guaranteed AC Performance over Temperature step is extremely linear and monotonic over the entire and Voltage: programming range, with 15 ps INL over temperature - >3.2 Gbps/1.6 GHz f MAX and voltage. Programming Accuracy: The delay varies in discrete steps based on a serial - Linearity: 15 ps to +15 ps INL control word provided by the 3-pin serial control - Monotonic: 5 ps to +25 ps (SDATA, SCLK, and SLOAD). The control word for - Resolution: 5 ps Programming Increments each channel is 10-bits. Both channels are Low-Jitter Design: 1 ps Typical Random Jitter programmed through a common serial interface. For RMS increased delay, multiple SY89297U delay lines can be Programmable Delay Range: 5 ns Delay Range cascaded together. Cascade Capability for Increased Delay The SY89297U provides two independent 3.2 Gbps Flexible Voltage Operation: delay lines in an ultra-small 4 mm x 4 mm, 24-pin QFN = 2.5V 5% or 3.3V 10% -V CC package. For other delay line solutions, consider the Industrial Temperature Range: 40C to +85C SY89295U and SY89296U single-channel delay lines. Available in 24-Lead (4 mm x 4 mm) QFN Evaluation boards are available for all these parts. Package Package Type Applications SY89297U Clock De-Skewing 24-Lead 4x4 QFN (M) Timing Adjustments Aperture Centering System Calibration 24 23 22 21 20 19 Markets 18 INA 1 QA Automated Test Equipment 2 17 /INA /QA Digital Radio and Video Broadcasting 16 3 VTA VCC Closed Caption Encoders/Decoders 15 VTB 4 VCC Test and Measurement 14 5 INB QB 6 13 /INB /QB 78 9 10 11 12 United States Patent No. RE44,134 2018 Microchip Technology Inc. DS20005835A-page 1 VREF-AC SLOAD GND SCLK /ENA SDATA /ENB SOUT GND GND VCC VCCSY89297U Functional Block Diagram INA CML 10 Bits QA VTA 5ps/Step = 5ns /QA /INA /ENA (TTL/CMOS) SLOAD LATCH B LATCH A Serial Interface SDATA SOUT D9B ... D1B D0B D9A ... D1A D0A SCLK TTL 20 Bits Open-Collector Resistor Pull-Up INB CML QB VTB 5ps/Step = 5ns /QB 10 Bits /INB /ENB VREF-AC DS20005835A-page 2 2018 Microchip Technology Inc.