Precision Edge 2.5V, 3.2Gbps DUAL, DIFFERENTIAL Micrel, Inc. SY89542U Precision Edge 2:1 LVDS MULTIPLEXER WITH SY89542U INTERNAL TERMINATION FEATURES Dual 2:1 multiplexer Precision Edge Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput DESCRIPTION < 600ps In-to-Out t pd < 150ps t /t r f The SY89542U includes two precision, high-speed 2:1 Ultra-low jitter design: differential Muxes with LVDS (350mV) compatible outputs < 1ps random jitter RMS with a guaranteed data rate throughput of 3.2Gbps over < 10ps deterministic jitter PP temperature and voltage. < 10ps total jitter (clock) PP The SY89542U differential inputs include a unique, 3-pin < 0.7ps crosstalk-induced jitter RMS internal termination that allows access to the termination Unique input isolation design minimizes crosstalk network through a V pin. This feature allows the device to T Internal input termination easily interface to different logic standards, both AC- and DC-coupled without external resistor-bias and termination Unique input termination and V pin accepts T networks. The result is a clean, stub-free, low jitter interface DC-Coupled and AC-coupled inputs (LVDS, LVPECL, solution. CML) The SY89542U operates from a single 2.5V supply, and 350mV LVDS output swing is guaranteed over the full industrial temperature range CMOS/TTL compatible MUX select (40C to +85C). For applications that require a 3.3V supply, Power supply 2.5V 5% consider the SY89543L. The SY89542U is part of Micrels 40C to +85C temperature range Precision Edge product family. Available in 32-pin (5mm x 5mm) MLF package All support documentation can be found on Micrels web site at www.micrel.com. APPLICATIONS Redundant clock/data switchover SONET/SDH multi-channel select applications Fibre Channel applications GigE applications FUNCTIONAL BLOCK DIAGRAM INA0 INB0 50 50 V V TA0 TB0 50 50 2:1 MUX 2:1 MUX /INA0 /INB0 0 0 LVDS LVDS QA QB MUX A MUX B /QA /QB 1 1 S S INA1 INB1 50 50 V V TA1 TB1 50 50 /INA1 /INB1 SELA (CMOS/TTL) SELB (CMOS/TTL) Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: D Amendment: /0 M9999-082407 1 Issue Date: August 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89542U PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish 1 24 VCC VCC SY89542UMI MLF-32 Industrial SY89542U Sn-Pb 23 /INA0 2 INB1 VTA0 3 22 VTB 1 (2) SY89542UMITR MLF-32 Industrial SY89542U Sn-Pb 4 21 INA0 /INB1 (3) 5 20 SY89542UMG MLF-32 Industrial SY89542U with Pb-Free VCC VCC SELA 6 19 SELB Pb-Free bar-line indicator NiPdAu GND 7 18 GND (2,3) SY89542UMGTR MLF-32 Industrial SY89542U with Pb-Free VCC 8 17 VCC 910 11 1213 14 1516 Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF 3. Recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 4, 2, 32, 30, INA0, /INA0, Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs 27, 25, 23, 21 INA1, /INA1, accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally INB0, /INB0, terminates to a V pin through 50 . Note that these inputs will default to an indeterminate T INB1, /INB1 state if left open. Unused differential input pairs can be terminated by connecting one input to V and the complementary input to GND through a 1k resistor. The V pin is to be CC T left open in this configuration. Please refer to the Input Interface Applications section for more details. 3, 31, 26, 22 VTA0 , VTA1, Input Termination Center-Tap: Each side of the differential input pair, terminates to a V T VTB0, VTB1 pin. The V , V , V , V pins provide a center-tap to a termination network for TA0 TA1 TB0 TB1 maximum interface flexibility. See Input Interface Applications section for more details. 6, 19 SELA, SELB These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. Input switching threshold is V /2. CC 1, 5, 8, 17, 20, VCC Positive Power Supply: Bypass with 0.1F 0.01F low ESR capacitors. The 0.01F 24, 28, 29 capacitor should be as close to V pin as possible. CC 10, 11, 14, 15 QA, /QA, Differential Outputs: This differential LVDS output pair provides a copy of the selected QB, /QB input. It is a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the Truth Table for details. Unused output pairs must be terminated with 100 across the differential pair. 7, 9, 12, 13, 16, 18 GND, Ground: Ground pin and exposed pad must be connected to the same ground plane. Exposed pad M9999-082407 2 hbwhelp micrel.com or (408) 955-1690 INA1 GND QA VTA1 /QA /INA1 GND VCC GND VCC QB INB0 /QB VTB0 /INB0 GND