MT40A1G16KNR-062E:E TR Micron

16Gb: x16 TwinDie Single Rank DDR4 SDRAM Description TwinDie 1.2V DDR4 SDRAM MT40A1G16 64 Meg x 16 x 16 Banks x 1 Ranks Options Marking Description Configuration The 16Gb (TwinDie) DDR4 SDRAM uses 64 Meg x 16 x 16 banks x 1 rank 1G16 Microns 8Gb DDR4 SDRAM die two x8s combined to 96-ball FBGA package (Pb-free) make one x16. Similar signals as mono x16, there is 9.5mm x 14mm x 1.2mm Die Rev :A HBA one extra ZQ connection for faster ZQ Calibration and 8.0mm x 14mm x 1.2mm Die Rev :B, WBU a BG1 control required for x8 addressing. Refer to Mi- D crons 8Gb DDR4 SDRAM data sheet (x8 option) for 7.5mm x 13.5mm x 1.2mm Die Rev :E KNR the specifications not included in this document. 1 Timing cycle time Specifications for base part number MT40A1G8 corre- 0.625ns CL = 22 (DDR4-3200) -062E late to TwinDie manufacturing part number 0.682ns CL = 21 (DDR4-2933) -068 MT40A1G16. 0.750ns CL = 19 (DDR4-2666) -075 0.750ns CL = 18 (DDR4-2666) -075E Features 0.833ns CL = 17(DDR4-2400) -083 Uses two x8 8Gb Micron die to make one x16 0.833ns CL = 16 (DDR4-2400) -083E Single rank TwinDie 0.937ns CL = 15 (DDR4-2133) -093E V = V = 1.2V (1.141.26V) DD DDQ 1.071ns CL = 13 (DDR4-1866) -107E 1.2V V -terminated I/O DDQ Self refresh JEDEC-standard ball-out Standard None Low-profile package Operating temperature T of 0C to 95C C Commercial (0C T 95C) None C 0C to 85C: 8192 refresh cycles in 64ms Revision :A 85C to 95C: 8192 refresh cycles in 32ms :B, D :E 1. CL = CAS (READ) latency. Note: Table 1: Key Timing Parameters 1 t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) -062Y 3200 22-22-22 13.75 (13.32) 13.75 (13.32) 13.75 (13.32) -062E 3200 22-22-22 13.75 13.75 13.75 -068 2933 21-21-21 14.32 (13.75) 14.32 (13.75) 14.32 (13.75) -075E 2666 18-18-18 13.50 13.50 13.50 -075 2666 19-19-19 14.25 14.25 14.25 -083E 2400 16-16-16 13.32 13.32 13.32 -083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75) -093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50) -093 2133 16-16-16 15.00 15.00 15.00 -107E 1866 13-13-13 13.92 (13.50) 13.92 (13.50) 13.92 (13.50) 1. Refer to Speed Bin Tables for additional details. Note: CCMTD-1725822587-9947 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 16gb x16 1cs TwinDie.pdf - Rev. G 06/18 EN 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.16Gb: x16 TwinDie Single Rank DDR4 SDRAM Description Table 2: Addressing Parameter 1024 Meg x 16 Configuration 64 Meg x 16 x 16 banks x 1 rank Bank group address BG 1:0 Bank count per group 4 Bank address in bank group BA 1:0 Row addressing 64K (A 15:0 ) Column addressing 1K (A 9:0 ) Page size 1KB Note: 1. Page size is per bank, calculated as follows: COLBITS Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. CCMTD-1725822587-9947 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 16gb x16 1cs TwinDie.pdf - Rev. G 06/18 EN 2015 Micron Technology, Inc. All rights reserved.