MT40A512M8SA-062E AIT:F Micron

4Gb: x8, x16 Automotive DDR4 SDRAM Features Automotive DDR4 SDRAM MT40A512M8 MT40A256M16 AEC-Q100 Features PPAP submission V = V = 1.2V 60mV DD DDQ 1 Options Marking V = 2.5V 125mV/+250mV PP Configuration On-die, internal, adjustable V generation REFDQ 512 Meg x 8 512M8 1.2V pseudo open-drain I/O 256 Meg x 16 256M16 Refresh maximum interval time at T temperature C BGA package (Pb-free) x8 range: 78-ball (9mm x 10.5mm) Rev. B RH 64ms at 40C to 85C 78-ball (7.5mm x 11mm) Rev. F SA 32ms at 85C to 95C FBGA package (Pb-free) x16 16ms at 96C to 105C 96-ball (9mm x 14mm) Rev. B GE 8ms at 106C to 125C 96-ball (7.5mm x 13.5mm) Rev. F LY 16 internal banks ( x8): 4 groups of 4 banks each Timing cycle time 8 internal banks (x16): 2 groups of 4 banks each 0.625ns CL = 22 (DDR4-3200) -062E 8n-bit prefetch architecture 0.750ns CL = 18 (DDR4-2666) -075E Programmable data strobe preambles 0.833ns CL = 16 (DDR4-2400) -083E Data strobe preamble training Product certification Command/Address latency (CAL) Automotive A Multipurpose register read and write capability Operating temperature Write leveling Industrial (40C T +95C) IT Self refresh mode C Automotive (40C T +105C) AT Low-power auto self refresh (LPASR) C 3 Ultra-high (40C T +125C) UT Temperature controlled refresh (TCR) C Revision :B :F Fine granularity refresh Self refresh abort 1. Not all options listed can be combined to Notes: Maximum power saving define an offered product. Use the part cat- Output driver calibration alog search on 4Gb: x8, x16 Automotive DDR4 SDRAM Features Table 1: Key Timing Parameters t t t Speed Grade Data Rate (MT/s) Target CL-nRCD-nRP AA (ns) RCD (ns) RP (ns) 1 -062E 3200 22-22-22 13.75 13.75 13.75 1 -075E 2666 18-18-18 13.5 13.5 13.5 -083E 2400 16-16-16 13.32 13.32 13.32 Note: 1. Refer to the Speed Bin Tables for backward compatibility Table 2: Addressing Parameter 512 Meg x 8 256 Meg x 16 Number of bank groups 4 2 Bank group address BG 1:0 BG0 Bank count per group 4 4 Bank address in bank group BA 1:0 BA 1:0 Row addressing 32K (A 14:0 ) 32K (A 14:0 ) Column addressing 1K (A 9:0 ) 1K (A 9:0 ) 1 Page size 1KB 2KB Note: 1. Page size is per bank, calculated as follows: COLBITS Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. CCMTD-1725822587-10418 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 4gb auto ddr4 sdram z90b z10B.pdf - Rev. K 12/2020 EN 2016 Micron Technology, Inc. All rights reserved.