MT42L32M32D1HE-18 AAT:D Micron

Preliminary 1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Features Automotive Mobile LPDDR2 SDRAM MT42L64M16D1, MT42L32M32D1 Options Marking Features V : 1.2V L DD2 Ultra low-voltage core and I/O power supplies Configuration V = 1.141.30V DD2 8 Meg x 16 x 8 banks x 1 die 64M16 V /V = 1.141.30V DDCA DDQ 4 Meg x 32 x 8 banks x 1 die 32M32 V = 1.701.95V DD1 Device type Clock frequency range LPDDR2-S4, 1 die in package D1 53310 MHz (data rate range: 106620 Mb/s/pin) FBGA green package Four-bit prefetch DDR architecture 134-ball FBGA (10mm x HE Eight internal banks for concurrent operation 11.5mm) Multiplexed, double data rate, command/address Timing cycle time inputs commands entered on every CK edge 1.875ns RL = 8 -18 Bidirectional/differential data strobe per byte of 2.5ns RL = 6 -25 data (DQS/DQS ) Special options Programmable READ and WRITE latencies (RL/WL) Automotive grade (Package-level A Programmable burst lengths: 4, 8, or 16 burn-in) Per-bank refresh for concurrent operation Operating temperature range On-chip temperature sensor to control self refresh From 40C to +85C IT rate From 40C to +105C AT Partial-array self refresh (PASR) Revision :A Deep power-down mode (DPD) t t 1. For Fast RCD/ RP, contact factory. Note: Selectable output drive strength (DS) Clock stop capability RoHS-compliant, green packaging Table 1: Key Timing Parameters Speed Clock Rate Data Rate t t 1 Grade (MHz) (Mb/s/pin) RL WL RCD/ RP -18 533 1066 8 4 Typical -25 400 800 6 3 Typical PDF: 09005aef85d5f0c6 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 1gb mobile lpddr2 u88m ait aat.pdf - Rev. B 12/14 EN 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Microns production data sheet specifications.Preliminary 1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Features Table 2: Single Channel S4 Configuration Addressing Architecture 64 Meg x 16 32 Meg x 32 Die 8 Meg x 16 x 8 banks 4 Meg x 32 x 8 banks configuration Row addressing 8K (A 12:0 ) 8K (A 12:0 ) Column 1K (A 9:0 ) 512 (A 8:0 ) addressing Number of die 1 1 Die per rank 1 1 1 Ranks per channel 11 Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins. PDF: 09005aef85d5f0c6 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 1gb mobile lpddr2 u88m ait aat.pdf - Rev. B 12/14 EN 2014 Micron Technology, Inc. All rights reserved.