256Mb: x4, x8, x16 Automotive SDRAM
Features
Automotive SDR SDRAM
MT48LC64M4A2 16 Meg x 4 x 4 banks
MT48LC32M8A2 8 Meg x 8 x 4 banks
MT48LC16M16A2 4 Meg x 16 x 4 banks
Options Marking
Features
1
54-pin TSOP II OCPL (400 mil) P
PC100- and PC133-compliant
Pb-free
Fully synchronous; all signals registered on positive
60-ball FBGA (x4, x8) (8mm x 16mm) FB
edge of system clock
60-ball FBGA (x4, x8) (8mm x 16mm) BB
Internal, pipelined operation; column address can
Pb-free
be changed every clock cycle
2
54-ball VFBGA (x16) (8mm x 14 mm) FG
Internal banks for hiding row access/precharge
2
54-ball VFBGA (x16) (8mm x 14 mm) BG
Programmable burst lengths: 1, 2, 4, 8, or full page
Pb-free
Auto precharge, includes concurrent auto precharge
3
54-ball VFBGA (x16) (8mm x 8 mm) F4
and auto refresh modes
3
54-ball VFBGA (x16) (8mm x 8 mm) B4
Self refresh mode (not available on AAT devices)
Pb-free
Auto refresh
Timing cycle time
64ms, 8192-cycle (commercial and industrial)
6ns @ CL = 3 (x8, x16 only) -6A
16ms, 8192-cycle (automotive)
7.5ns @ CL = 3 (PC133) -75
LVTTL-compatible inputs and outputs
7.5ns @ CL = 2 (PC133) -7E
Single 3.3V 0.3V power supply
Self refresh
AEC-Q100
Standard None
PPAP submission
4
Low power L
8D response time
Operating temperature range
Industrial (40C to +85C) AIT
Options Marking
4
Automotive (40C to +105C) AAT
Configurations
Revision :D/:G
64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4
32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8
1. Off-center parting line.
Notes:
16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16
2. Only available on Revision D.
t
Write recovery ( WR)
3. Only available on Revision G.
t
WR = 2 CLK A2
4. Contact Micron for availability.
1
Plastic package OCPL
1
54-pin TSOP II OCPL (400 mil) TG
(standard)
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Access Time
Clock
Speed Grade Frequency CL = 2 CL = 3 Setup Time Hold Time
-6A 167 MHz 5.4ns 1.5ns 0.8ns
-7E 143 MHz 5.4ns 1.5ns 0.8ns
-75 133 MHz 5.4ns 1.5ns 0.8ns
-7E 133 MHz 5.4ns 1.5ns 0.8ns
-75 100 MHz 6ns 1.5ns 0.8ns
09005aef848d99e8 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
256Mb_ait_aat_sdr_esg.pdf - Rev. D 6/18 EN 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.256Mb: x4, x8, x16 Automotive SDRAM
Features
Table 2: Address Table
16 Meg
Parameter 64 Meg x 4 32 Meg x 8 x 16
Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
Refresh count 8K 8K 8K
Row addressing 8K A[12:0] 8K A[12:0] 8K A[12:0]
Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0]
Column 2K A[9:0, 11] 1K A[9:0] 512 A[8:0]
addressing
Table 3: 256Mb SDR Part Numbering
Part Numbers Architecture Package
MT48LC64M4A2TG 64 Meg x 4 54-pin TSOP II
MT48LC64M4A2P 64 Meg x 4 54-pin TSOP II
1
MT48LC64M4A2FB 64 Meg x 4 60-ball FBGA
1
MT48LC64M4A2BB 64 Meg x 4 60-ball FBGA
MT48LC32M8A2TG 32 Meg x 8 54-pin TSOP II
MT48LC32M8A2P 32 Meg x 8 54-pin TSOP II
1
MT48LC32M8A2FB 32 Meg x 8 60-ball FBGA
1
MT48LC32M8A2BB 32 Meg x 8 60-ball FBGA
MT48LC16M16A2TG 16 Meg x 16 54-pin TSOP II
MT48LC16M16A2P 16 Meg x 16 54-pin TSOP II
MT48LC16M16A2FG 16 Meg x 16 54-ball FBGA
MT48LC16M16A2BG 16 Meg x 16 54-ball FBGA
Note: 1. FBGA Device Decoder: www.micron.com/decoder.
09005aef848d99e8 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
256Mb_ait_aat_sdr_esg.pdf - Rev. D 6/18 EN 2012 Micron Technology, Inc. All rights reserved.