Micron Confidential and Proprietary 200b: x32 LPDDR4/LPDDR4X SDRAM Features LPDDR4/LPDDR4X SDRAM MT53D512M32D2, MT53D1024M32D4 Options Marking Features V /V /V : 1.80V/1.10V/1.10V or D DD1 DD2 DDQ This datasheet is for LPDDR4 and LPDDR4X unified 0.60V product based on LPDDR4X information. Refer to Array configuration LPDDR4 setting section LPDDR4 1.10V V at the DDQ 512 Meg 32 (2 channels 16 I/O) 512M32 end of this datasheet. 1024 Meg 32 (2 channels 16 I/O) 1024M32 Device configuration Ultra-low-voltage core and I/O power supplies 512M16 2 die in package D2 V = 1.701.95V 1.80V nominal DD1 512M16 4 die in package D4 V = 1.061.17V 1.10V nominal DD2 FBGA green package V = 1.061.17V 1.10V nominal DDQ 200-ball WFBGA (10mm 14.5mm DS or Low V = 0.570.65V 0.60V nominal DDQ 0.8mm, 0.35 SMD) Frequency range 200-ball VFBGA (10mm 14.5mm DT 213310 MHz (data rate range: 426620 Mb/s/ 0.95mm, 0.35 SMD) pin) Speed grade, cycle time 16n prefetch DDR architecture 535ps RL = 32/36 -053 8 internal banks per channel for concurrent opera- 468ps RL = 36/40 -046 tion Operating temperature range Single-data-rate CMD/ADR entry 25C to +85C WT Bidirectional/differential data strobe per byte lane Revision :D Programmable READ and WRITE latencies (RL/WL) Programmable and on-the-fly burst lengths (BL = 16, 32) Directed per-bank refresh for concurrent bank op- eration and ease of command scheduling Up to 8.5 GB/s per die On-chip temperature sensor to control self refresh rate Partial-array self refresh (PASR) Selectable output drive strength (DS) Clock-stop capability RoHS-compliant, green packaging Programmable V (ODT) termination SS Table 1: Key Timing Parameters WRITE Latency READ Latency Speed Clock Rate Data Rate Grade (MHz) (Mb/s/pin) Set A Set B DBI Disabled DBI Enabled -053 1866 3733 16 30 32 36 -046 2133 4266 18 34 36 40 CCM005-554574167-10522 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 200b z11m non-auto lpddr4 lpddr4x.pdf Rev. A 11/17 EN 2017 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.Micron Confidential and Proprietary 200b: x32 LPDDR4/LPDDR4X SDRAM Features SDRAM Addressing The table below shows the addressing for the 8Gb die density. Where applicable, a distinction is made between per-channel and per-die parameters. All bank, row, and column addresses are shown per-channel. Table 2: SDRAM Addressing Configuration 512M32 (16Gb) 1024M32 (32Gb) Die per package 2 4 Device density (per die) 8Gb 8Gb Device density (per channel) 8Gb 8Gb Configuration 64Mb x 16 DQ x 8 banks 64Mb x 16 DQ x 8 banks x 2 channels x 1 rank x 2 channels x 2 ranks Number of channels (per die) 1 1 Number of ranks per channel 1 2 Number of banks (per channel) 8 8 Array prefetch (bits) (per channel) 256 256 Number of rows (per bank) 65,536 65,536 Number of columns (fetch boundaries) 64 64 Page size (bytes) 2048 2048 Channel density (bits per channel) 8,589,934,592 17,179,869,184 Total density (bits per die) 8,589,934,592 8,589,934,592 Bank address BA 2:0 BA 2:0 x16 Row addresses R 15:0 R 15:0 Column addresses C 9:0 C 9:0 Burst starting address boundary 64-bit 64-bit Notes: 1. The lower two column addresses (C 1:0 ) are assumed to be zero and are not transmitted on the CA bus. 2. Row and column address values on the CA bus that are not used for a particular density areDon t Care 3. For non-binary memory densities, only quarter of the row address space is invalid. When the MSB address bit is HIGH, the MSB - 1 address bit must be LOW. CCM005-554574167-10522 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 200b z11m non-auto lpddr4 lpddr4x.pdf Rev. A 11/17 EN 2017 Micron Technology, Inc. All rights reserved.